Messages in this thread | | | From | Aisheng Dong <> | Subject | RE: [PATCH v2] clk: imx: Refactor entire sccg pll clk | Date | Tue, 26 Feb 2019 11:18:08 +0000 |
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> From: Stephen Boyd [mailto:sboyd@kernel.org] > Sent: Tuesday, February 26, 2019 1:23 AM> > Quoting Abel Vesa (2019-02-23 02:58:14) > > On 19-02-22 09:46:23, Stephen Boyd wrote: > > > Quoting Abel Vesa (2019-02-22 09:07:32) > > > > Make the entire combination of plls to be one single clock. The > > > > parents used for bypasses are specified each as an index in the parents > list. > > > > The determine_rate does a lookup throughout all the possible > > > > combinations for all the divs and returns the best possible > > > > 'setup' which in turn is used by set_rate later to set up all the divs and > bypasses. > > > > > > > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
This significantly simply the clock tree output. Thanks for the work.
> > > > Tested-by: Lucas Stach <l.stach@pengutronix.de> > > > > Acked-by: Lucas Stach <l.stach@pengutronix.de> > > > > > > I suspect these tested by and acked tags should have been dropped, > > > unless you discussed and tested off-list? > > > > > > > Oups, I forgot to drop them. > > Ok. Can Lucas re-test?
Tested on clk-next by cherry-pick a few defconfig patches from imx tree. So: Tested-by: Dong Aisheng <aisheng.dong@nxp.com>
Regards Dong Aisheng
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