Messages in this thread Patch in this message | | | From | wangyan wang <> | Subject | [PATCH V6 4/8] drm/mediatek: fix the rate and divder of hdmi phy for MT2701 | Date | Mon, 25 Feb 2019 10:09:08 +0800 |
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From: chunhui dai <chunhui.dai@mediatek.com>
Due to a clerical error,there is one zero less for 12800000. Fix it for 128000000.
Fixes: 0fc721b2968e ("drm/mediatek: add hdmi driver for MT2701 and MT7623")
Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: chunhui dai <chunhui.dai@mediatek.com> Signed-off-by: wangyan wang <wangyan.wang@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c index 43bc058d5528..88dd9e812ca0 100644 --- a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c +++ b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c @@ -114,8 +114,8 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, if (rate <= 64000000) pos_div = 3; - else if (rate <= 12800000) - pos_div = 1; + else if (rate <= 128000000) + pos_div = 2; else pos_div = 1; -- 2.14.1
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