Messages in this thread | | | Subject | Re: [RESEND] clk: imx: Refactor entire sccg pll clk | From | Stephen Boyd <> | Date | Thu, 21 Feb 2019 12:43:58 -0800 |
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Quoting Abel Vesa (2019-02-18 01:24:33) > Make the entire combination of plls to be one single clock. The parents used > for bypasses are specified each as an index in the parents list. > The determine_rate does a lookup throughout all the possible combinations > for all the divs and returns the best possible 'setup' which in turn is used > by set_rate later to set up all the divs and bypasses. > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > Tested-by: Lucas Stach <l.stach@pengutronix.de> > Acked-by: Lucas Stach <l.stach@pengutronix.de> > ---
Applied to clk-next
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