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SubjectRe: [PATCH 02/10] powerpc/603: Store PGDIR physical address in a SPRG
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Le 25/01/2019 à 13:34, Christophe Leroy a écrit :
> Use SPRN_SPRG5 to store the current thread PGDIR and
> avoid reading thread_struct->pgdir at every TLB miss.

I'll send out v2 with an additional patch getting rid of SPRN_SPRG_RTAS
hence freeing SPRN_SPRG2 which I will use here instead of SPRN_SPRG5 so
that all 6xx will benefit.

Christophe

>
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
> ---
> arch/powerpc/include/asm/reg.h | 1 +
> arch/powerpc/kernel/cpu_setup_6xx.S | 4 ++++
> arch/powerpc/kernel/head_32.S | 28 ++++++++++++++++------------
> 3 files changed, 21 insertions(+), 12 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
> index 1c98ef1f2d5b..ba0ab1a1431b 100644
> --- a/arch/powerpc/include/asm/reg.h
> +++ b/arch/powerpc/include/asm/reg.h
> @@ -1169,6 +1169,7 @@
> #define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
> #define SPRN_SPRG_RTAS SPRN_SPRG2
> #define SPRN_SPRG_603_LRU SPRN_SPRG4
> +#define SPRN_SPRG_603_PGDIR SPRN_SPRG5
> #endif
>
> #ifdef CONFIG_40x
> diff --git a/arch/powerpc/kernel/cpu_setup_6xx.S b/arch/powerpc/kernel/cpu_setup_6xx.S
> index 8c069e96c478..4c91d1f640fe 100644
> --- a/arch/powerpc/kernel/cpu_setup_6xx.S
> +++ b/arch/powerpc/kernel/cpu_setup_6xx.S
> @@ -24,6 +24,10 @@ BEGIN_MMU_FTR_SECTION
> li r10,0
> mtspr SPRN_SPRG_603_LRU,r10 /* init SW LRU tracking */
> END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
> + lis r10, (swapper_pg_dir - PAGE_OFFSET)@h
> + ori r10, r10, (swapper_pg_dir - PAGE_OFFSET)@l
> + mtspr SPRN_SPRG_603_PGDIR, r10
> +
> BEGIN_FTR_SECTION
> bl __init_fpu_registers
> END_FTR_SECTION_IFCLR(CPU_FTR_FPU_UNAVAILABLE)
> diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
> index c2f564690778..dbd15e03952a 100644
> --- a/arch/powerpc/kernel/head_32.S
> +++ b/arch/powerpc/kernel/head_32.S
> @@ -502,16 +502,15 @@ InstructionTLBMiss:
> mfspr r3,SPRN_IMISS
> lis r1,PAGE_OFFSET@h /* check if kernel address */
> cmplw 0,r1,r3
> - mfspr r2,SPRN_SPRG_THREAD
> + mfspr r2, SPRN_SPRG_603_PGDIR
> li r1,_PAGE_USER|_PAGE_PRESENT|_PAGE_EXEC /* low addresses tested as user */
> - lwz r2,PGDIR(r2)
> bge- 112f
> mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
> rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
> lis r2,swapper_pg_dir@ha /* if kernel address, use */
> addi r2,r2,swapper_pg_dir@l /* kernel page table */
> -112: tophys(r2,r2)
> - rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
> + tophys(r2,r2)
> +112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
> lwz r2,0(r2) /* get pmd entry */
> rlwinm. r2,r2,0,0,19 /* extract address of pte page */
> beq- InstructionAddressInvalid /* return if no mapping */
> @@ -576,16 +575,15 @@ DataLoadTLBMiss:
> mfspr r3,SPRN_DMISS
> lis r1,PAGE_OFFSET@h /* check if kernel address */
> cmplw 0,r1,r3
> - mfspr r2,SPRN_SPRG_THREAD
> + mfspr r2, SPRN_SPRG_603_PGDIR
> li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
> - lwz r2,PGDIR(r2)
> bge- 112f
> mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
> rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
> lis r2,swapper_pg_dir@ha /* if kernel address, use */
> addi r2,r2,swapper_pg_dir@l /* kernel page table */
> -112: tophys(r2,r2)
> - rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
> + tophys(r2,r2)
> +112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
> lwz r2,0(r2) /* get pmd entry */
> rlwinm. r2,r2,0,0,19 /* extract address of pte page */
> beq- DataAddressInvalid /* return if no mapping */
> @@ -660,16 +658,15 @@ DataStoreTLBMiss:
> mfspr r3,SPRN_DMISS
> lis r1,PAGE_OFFSET@h /* check if kernel address */
> cmplw 0,r1,r3
> - mfspr r2,SPRN_SPRG_THREAD
> + mfspr r2, SPRN_SPRG_603_PGDIR
> li r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */
> - lwz r2,PGDIR(r2)
> bge- 112f
> mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
> rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
> lis r2,swapper_pg_dir@ha /* if kernel address, use */
> addi r2,r2,swapper_pg_dir@l /* kernel page table */
> -112: tophys(r2,r2)
> - rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
> + tophys(r2,r2)
> +112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
> lwz r2,0(r2) /* get pmd entry */
> rlwinm. r2,r2,0,0,19 /* extract address of pte page */
> beq- DataAddressInvalid /* return if no mapping */
> @@ -1030,6 +1027,13 @@ _ENTRY(switch_mmu_context)
> lis r5, abatron_pteptrs@ha
> stw r4, abatron_pteptrs@l + 0x4(r5)
> #endif
> +BEGIN_MMU_FTR_SECTION
> +#ifndef CONFIG_BDI_SWITCH
> + lwz r4, MM_PGD(r4)
> +#endif
> + tophys(r4, r4)
> + mtspr SPRN_SPRG_603_PGDIR, r4
> +END_MMU_FTR_SECTION_IFCLR(MMU_FTR_HPTE_TABLE)
> li r4,0
> isync
> 3:
>

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