Messages in this thread Patch in this message | | | From | <> | Subject | [PATCH 7/7] clk: stm32mp1: fix bit width of hse_rtc divider | Date | Tue, 12 Feb 2019 14:51:54 +0100 |
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From: Gabriel Fernandez <gabriel.fernandez@st.com>
This patch fixes the bit width of the hse rtc divider.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> --- drivers/clk/clk-stm32mp1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c index 6c99950c6135..fc75cf12f0e5 100644 --- a/drivers/clk/clk-stm32mp1.c +++ b/drivers/clk/clk-stm32mp1.c @@ -1961,7 +1961,7 @@ static const struct clock_config stm32mp1_clock_cfg[] = { _DIV(RCC_ETHCKSELR, 4, 4, 0, NULL)), /* RTC clock */ - DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 7, 0), + DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 6, 0), COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_PARENT, -- 2.17.0
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