Messages in this thread | | | Subject | Re: [PATCH net-next 4/4] net: phy: Add generic support for 2.5GBaseT and 5GBaseT | From | Heiner Kallweit <> | Date | Tue, 12 Feb 2019 20:14:53 +0100 |
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On 11.02.2019 15:25, Maxime Chevallier wrote: > The 802.3bz specification, based on previous by the NBASET alliance, > defines the 2.5GBaseT and 5GBaseT link modes for ethernet traffic on > cat5e, cat6 and cat7 cables. > > These mode integrate with the already defined C45 MDIO PMA/PMD registers > set that added 10G support, by defining some previously reserved bits, > and adding a new register (2.5G/5G Extended abilities). > > This commit adds the required definitions in include/uapi/linux/mdio.h > to support these modes, and detect when a link-partner advertises them. > > It also adds support for these mode in the generic C45 PHY > infrastructure. > > Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> > --- > drivers/net/phy/phy-c45.c | 37 +++++++++++++++++++++++++++++++++++++ > include/uapi/linux/mdio.h | 16 ++++++++++++++++ > 2 files changed, 53 insertions(+) > > diff --git a/drivers/net/phy/phy-c45.c b/drivers/net/phy/phy-c45.c > index 6f028de4dae1..7af5fa81daf6 100644 > --- a/drivers/net/phy/phy-c45.c > +++ b/drivers/net/phy/phy-c45.c > @@ -47,6 +47,16 @@ int genphy_c45_pma_setup_forced(struct phy_device *phydev) > /* Assume 1000base-T */ > ctrl2 |= MDIO_PMA_CTRL2_1000BT; > break; > + case SPEED_2500: > + ctrl1 |= MDIO_CTRL1_SPEED2_5G; > + /* Assume 2.5Gbase-T */ > + ctrl2 |= MDIO_PMA_CTRL2_2_5GBT; > + break; > + case SPEED_5000: > + ctrl1 |= MDIO_CTRL1_SPEED5G; > + /* Assume 5Gbase-T */ > + ctrl2 |= MDIO_PMA_CTRL2_5GBT; > + break; > case SPEED_10000: > ctrl1 |= MDIO_CTRL1_SPEED10G; > /* Assume 10Gbase-T */ > @@ -194,6 +204,12 @@ int genphy_c45_read_lpa(struct phy_device *phydev) > if (val < 0) > return val; > > + if (val & MDIO_AN_10GBT_STAT_LP2_5G) > + linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, > + phydev->lp_advertising); > + if (val & MDIO_AN_10GBT_STAT_LP5G) > + linkmode_set_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, > + phydev->lp_advertising); > if (val & MDIO_AN_10GBT_STAT_LP10G) > linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, > phydev->lp_advertising); > @@ -224,6 +240,12 @@ int genphy_c45_read_pma(struct phy_device *phydev) > case MDIO_PMA_CTRL1_SPEED1000: > phydev->speed = SPEED_1000; > break; > + case MDIO_CTRL1_SPEED2_5G: > + phydev->speed = SPEED_2500; > + break; > + case MDIO_CTRL1_SPEED5G: > + phydev->speed = SPEED_5000; > + break; > case MDIO_CTRL1_SPEED10G: > phydev->speed = SPEED_10000; > break; > @@ -339,6 +361,21 @@ int genphy_c45_pma_read_abilities(struct phy_device *phydev) > linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, > phydev->supported, > val & MDIO_PMA_EXTABLE_10BT); > + > + if (val & MDIO_PMA_EXTABLE_NBT) { > + val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, > + MDIO_PMA_NG_EXTABLE); > + if (val < 0) > + return val; > + > + linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, > + phydev->supported, > + val & MDIO_PMA_NG_EXTABLE_2_5GBT); > + > + linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, > + phydev->supported, > + val & MDIO_PMA_NG_EXTABLE_5GBT); > + } > } > > return 0; > diff --git a/include/uapi/linux/mdio.h b/include/uapi/linux/mdio.h > index 0e012b168e4d..0a552061ff1c 100644 > --- a/include/uapi/linux/mdio.h > +++ b/include/uapi/linux/mdio.h > @@ -45,6 +45,7 @@ > #define MDIO_AN_ADVERTISE 16 /* AN advertising (base page) */ > #define MDIO_AN_LPA 19 /* AN LP abilities (base page) */ > #define MDIO_PCS_EEE_ABLE 20 /* EEE Capability register */ > +#define MDIO_PMA_NG_EXTABLE 21 /* 2.5G/5G PMA/PMD extended ability */ > #define MDIO_PCS_EEE_WK_ERR 22 /* EEE wake error counter */ > #define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */ > #define MDIO_AN_EEE_ADV 60 /* EEE advertisement */ > @@ -92,6 +93,10 @@ > #define MDIO_CTRL1_SPEED10G (MDIO_CTRL1_SPEEDSELEXT | 0x00) > /* 10PASS-TS/2BASE-TL */ > #define MDIO_CTRL1_SPEED10P2B (MDIO_CTRL1_SPEEDSELEXT | 0x04) > +/* 2.5 Gb/s */ > +#define MDIO_CTRL1_SPEED2_5G (MDIO_CTRL1_SPEEDSELEXT | 0x18) > +/* 5 Gb/s */ > +#define MDIO_CTRL1_SPEED5G (MDIO_CTRL1_SPEEDSELEXT | 0x1c) > > /* Status register 1. */ > #define MDIO_STAT1_LPOWERABLE 0x0002 /* Low-power ability */ > @@ -145,6 +150,8 @@ > #define MDIO_PMA_CTRL2_1000BKX 0x000d /* 1000BASE-KX type */ > #define MDIO_PMA_CTRL2_100BTX 0x000e /* 100BASE-TX type */ > #define MDIO_PMA_CTRL2_10BT 0x000f /* 10BASE-T type */ > +#define MDIO_PMA_CTRL2_2_5GBT 0x0030 /* 2.5GBaseT type */ > +#define MDIO_PMA_CTRL2_5GBT 0x0031 /* 5GBaseT type */ > #define MDIO_PCS_CTRL2_TYPE 0x0003 /* PCS type selection */ > #define MDIO_PCS_CTRL2_10GBR 0x0000 /* 10GBASE-R type */ > #define MDIO_PCS_CTRL2_10GBX 0x0001 /* 10GBASE-X type */ > @@ -198,6 +205,7 @@ > #define MDIO_PMA_EXTABLE_1000BKX 0x0040 /* 1000BASE-KX ability */ > #define MDIO_PMA_EXTABLE_100BTX 0x0080 /* 100BASE-TX ability */ > #define MDIO_PMA_EXTABLE_10BT 0x0100 /* 10BASE-T ability */ > +#define MDIO_PMA_EXTABLE_NBT 0x4000 /* 2.5/5GBASE-T ability */ > > /* PHY XGXS lane state register. */ > #define MDIO_PHYXS_LNSTAT_SYNC0 0x0001 > @@ -234,9 +242,13 @@ > #define MDIO_PCS_10GBRT_STAT2_BER 0x3f00 > > /* AN 10GBASE-T control register. */ > +#define MDIO_AN_10GBT_CTRL_ADV2_5G 0x0080 /* Advertise 2.5GBASE-T */ > +#define MDIO_AN_10GBT_CTRL_ADV5G 0x0100 /* Advertise 5GBASE-T */ > #define MDIO_AN_10GBT_CTRL_ADV10G 0x1000 /* Advertise 10GBASE-T */ > > /* AN 10GBASE-T status register. */ > +#define MDIO_AN_10GBT_STAT_LP2_5G 0x0020 /* LP is 2.5GBT capable */ > +#define MDIO_AN_10GBT_STAT_LP5G 0x0040 /* LP is 5GBT capable */ > #define MDIO_AN_10GBT_STAT_LPTRR 0x0200 /* LP training reset req. */ > #define MDIO_AN_10GBT_STAT_LPLTABLE 0x0400 /* LP loop timing ability */ > #define MDIO_AN_10GBT_STAT_LP10G 0x0800 /* LP is 10GBT capable */ > @@ -265,6 +277,10 @@ > #define MDIO_EEE_10GKX4 0x0020 /* 10G KX4 EEE cap */ > #define MDIO_EEE_10GKR 0x0040 /* 10G KR EEE cap */ > > +/* 2.5G/5G Extended abilities register. */ > +#define MDIO_PMA_NG_EXTABLE_2_5GBT 0x0001 /* 2.5GBASET ability */ > +#define MDIO_PMA_NG_EXTABLE_5GBT 0x0002 /* 5GBASET ability */ > + > /* LASI RX_ALARM control/status registers. */ > #define MDIO_PMA_LASI_RX_PHYXSLFLT 0x0001 /* PHY XS RX local fault */ > #define MDIO_PMA_LASI_RX_PCSLFLT 0x0008 /* PCS RX local fault */ > Looks good to me.
Reviewed-by: Heiner Kallweit <hkallweit1@gmail.com>
Heiner
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