lkml.org 
[lkml]   [2019]   [Feb]   [11]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH 4.20 009/352] drm/sun4i: Initialize registers in tcon-top driver
    Date
    4.20-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    [ Upstream commit c96d62215fb540e2ae61de44cb7caf4db50958e3 ]

    It turns out that TCON TOP registers in H6 SoC have non-zero reset
    value. This may cause issues if bits are not changed during
    configuration.

    To prevent that, initialize registers to 0.

    Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
    Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20181104182705.18047-24-jernej.skrabec@siol.net
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 7 +++++++
    1 file changed, 7 insertions(+)

    diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
    index 3040a79f298f..37158548b447 100644
    --- a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
    +++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
    @@ -167,6 +167,13 @@ static int sun8i_tcon_top_bind(struct device *dev, struct device *master,
    goto err_assert_reset;
    }

    + /*
    + * At least on H6, some registers have some bits set by default
    + * which may cause issues. Clear them here.
    + */
    + writel(0, regs + TCON_TOP_PORT_SEL_REG);
    + writel(0, regs + TCON_TOP_GATE_SRC_REG);
    +
    /*
    * TCON TOP has two muxes, which select parent clock for each TCON TV
    * channel clock. Parent could be either TCON TV or TVE clock. For now
    --
    2.19.1


    \
     
     \ /
      Last update: 2019-02-11 17:15    [W:4.787 / U:25.848 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site