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    Subject[PATCH 4.20 146/352] clk: imx6sl: ensure MMDC CH0 handshake is bypassed
    Date
    4.20-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    [ Upstream commit 0efcc2c0fd2001a83240a8c3d71f67770484917e ]

    Same as other i.MX6 SoCs, ensure unused MMDC channel's
    handshake is bypassed, this is to make sure no request
    signal will be generated when periphe_clk_sel is changed
    or SRC warm reset is triggered.

    Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
    Signed-off-by: Stephen Boyd <sboyd@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/clk/imx/clk-imx6sl.c | 6 ++++++
    1 file changed, 6 insertions(+)

    diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c
    index 6fcfbbd907a5..e13d8814cfa4 100644
    --- a/drivers/clk/imx/clk-imx6sl.c
    +++ b/drivers/clk/imx/clk-imx6sl.c
    @@ -17,6 +17,8 @@

    #include "clk.h"

    +#define CCDR 0x4
    +#define BM_CCM_CCDR_MMDC_CH0_MASK (1 << 17)
    #define CCSR 0xc
    #define BM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
    #define CACRR 0x10
    @@ -411,6 +413,10 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
    clks[IMX6SL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
    clks[IMX6SL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);

    + /* Ensure the MMDC CH0 handshake is bypassed */
    + writel_relaxed(readl_relaxed(base + CCDR) |
    + BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR);
    +
    imx_check_clocks(clks, ARRAY_SIZE(clks));

    clk_data.clks = clks;
    --
    2.19.1


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