Messages in this thread | | | Subject | Re: [PATCH v3 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem | From | Luca Ceresoli <> | Date | Mon, 11 Feb 2019 15:30:47 +0100 |
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Hi,
thanks for the quick reply.
On 11/02/19 13:43, Vishal Sagar wrote: >>> +static int xcsi2rxss_start_stream(struct xcsi2rxss_state *state) >>> +{ >>> + struct xcsi2rxss_core *core = &state->core; >>> + int ret = 0; >>> + >>> + xcsi2rxss_enable(core); >>> + >>> + ret = xcsi2rxss_reset(core); >>> + if (ret < 0) { >>> + state->streaming = false; >>> + return ret; >>> + } >>> + >>> + xcsi2rxss_intr_enable(core); >>> + state->streaming = true; >> >> Shouldn't you propagate s_stream to the upstream subdev here calling >> v4l2_subdev_call(..., ..., s_stream, 1)? >> > > This is done by the xvip_pipeline_start_stop() in xilinx-dma.c for Xilinx Video pipeline.
Indeed it does, however other CSI2 RX drivers do propagate s_stream in their own s_stream. Not strictly related to this driver, but what's the logic for having these two different behaviors?
Also xvip_pipeline_start_stop() only follows the graph through entity->pads[0], so it looks like it cannot handle entities with multiple sink pads. How would it be able to handle e.g. the AXI4-Stream Switch [0], which has 2+ sink pads?
[0] https://www.xilinx.com/support/documentation/ip_documentation/axis_infrastructure_ip_suite/v1_1/pg085-axi4stream-infrastructure.pdf (page 16).
-- Luca
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