Messages in this thread | | | Subject | Re: [PATCH 3/3] mtd: spi-nor: Add USE_FSR flag for n25q* entries | From | John Garry <> | Date | Thu, 5 Dec 2019 11:21:20 +0000 |
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On 05/12/2019 06:59, Vignesh Raghavendra wrote: > Add USE_FSR flag to all variants of n25q entries that support Flag Status > Register. > > Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: John Garry <john.garry@huawei.com> #for n25q128a13
> --- > drivers/mtd/spi-nor/spi-nor.c | 15 ++++++++++----- > 1 file changed, 10 insertions(+), 5 deletions(-) > > diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c > index a5cb647378f0..1082b6bb1393 100644 > --- a/drivers/mtd/spi-nor/spi-nor.c > +++ b/drivers/mtd/spi-nor/spi-nor.c > @@ -2454,16 +2454,21 @@ static const struct flash_info spi_nor_ids[] = { > { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, > { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, > { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, > - { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, > - { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, > + { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | > + USE_FSR | SPI_NOR_QUAD_READ) }, > + { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | > + USE_FSR | SPI_NOR_QUAD_READ) }, > { "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512, > SECT_4K | USE_FSR | SPI_NOR_DUAL_READ | > SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, > - { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, > + { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | > + USE_FSR | SPI_NOR_DUAL_READ | > + SPI_NOR_QUAD_READ) }, > { "mt25qu256a", INFO6(0x20bb19, 0x104400, 64 * 1024, 512, > SECT_4K | USE_FSR | SPI_NOR_DUAL_READ | > SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, > - { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, > + { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | > + USE_FSR | SPI_NOR_QUAD_READ) }, > { "mt25ql512a", INFO6(0x20ba20, 0x104400, 64 * 1024, 1024, > SECT_4K | USE_FSR | SPI_NOR_DUAL_READ | > SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, > @@ -2472,7 +2477,7 @@ static const struct flash_info spi_nor_ids[] = { > SECT_4K | USE_FSR | SPI_NOR_DUAL_READ | > SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, > { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | > - SPI_NOR_QUAD_READ) }, > + USE_FSR | SPI_NOR_QUAD_READ) }, > { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, > { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, > { "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096, >
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