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    Subject[PATCH 4.14 009/209] clk: sunxi-ng: a80: fix the zeroing of bits 16 and 18
    Date
    From: Colin Ian King <colin.king@canonical.com>

    [ Upstream commit cdfc2e2086bf9c465f44e2db25561373b084a113 ]

    The zero'ing of bits 16 and 18 is incorrect. Currently the code
    is masking with the bitwise-and of BIT(16) & BIT(18) which is
    0, so the updated value for val is always zero. Fix this by bitwise
    and-ing value with the correct mask that will zero bits 16 and 18.

    Addresses-Coverity: (" Suspicious &= or |= constant expression")
    Fixes: b8eb71dcdd08 ("clk: sunxi-ng: Add A80 CCU")
    Signed-off-by: Colin Ian King <colin.king@canonical.com>
    Signed-off-by: Maxime Ripard <mripard@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/clk/sunxi-ng/ccu-sun9i-a80.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80.c b/drivers/clk/sunxi-ng/ccu-sun9i-a80.c
    index 8936ef87652c0..c14bf782b2b33 100644
    --- a/drivers/clk/sunxi-ng/ccu-sun9i-a80.c
    +++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80.c
    @@ -1231,7 +1231,7 @@ static int sun9i_a80_ccu_probe(struct platform_device *pdev)

    /* Enforce d1 = 0, d2 = 0 for Audio PLL */
    val = readl(reg + SUN9I_A80_PLL_AUDIO_REG);
    - val &= (BIT(16) & BIT(18));
    + val &= ~(BIT(16) | BIT(18));
    writel(val, reg + SUN9I_A80_PLL_AUDIO_REG);

    /* Enforce P = 1 for both CPU cluster PLLs */
    --
    2.20.1


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