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    Subject[PATCH 5.4 288/434] ASoC: rt5677: Mark reg RT5677_PWR_ANLG2 as volatile
    Date
    From: Ben Zhang <benzh@chromium.org>

    [ Upstream commit eabf424f7b60246c76dcb0ea6f1e83ef9abbeaa6 ]

    The codec dies when RT5677_PWR_ANLG2(MX-64h) is set to 0xACE1
    while it's streaming audio over SPI. The DSP firmware turns
    on PLL2 (MX-64 bit 8) when SPI streaming starts. However regmap
    does not believe that register can change by itself. When
    BST1 (bit 15) is turned on with regmap_update_bits(), it doesn't
    read the register first before write, so PLL2 power bit is
    cleared by accident.

    Marking MX-64h as volatile in regmap solved the issue.

    Signed-off-by: Ben Zhang <benzh@chromium.org>
    Signed-off-by: Curtis Malainey <cujomalainey@chromium.org>
    Link: https://lore.kernel.org/r/20191106011335.223061-6-cujomalainey@chromium.org
    Signed-off-by: Mark Brown <broonie@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    sound/soc/codecs/rt5677.c | 1 +
    1 file changed, 1 insertion(+)

    diff --git a/sound/soc/codecs/rt5677.c b/sound/soc/codecs/rt5677.c
    index 315a3d39bc09..8bc9450da79c 100644
    --- a/sound/soc/codecs/rt5677.c
    +++ b/sound/soc/codecs/rt5677.c
    @@ -298,6 +298,7 @@ static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
    case RT5677_I2C_MASTER_CTRL7:
    case RT5677_I2C_MASTER_CTRL8:
    case RT5677_HAP_GENE_CTRL2:
    + case RT5677_PWR_ANLG2: /* Modified by DSP firmware */
    case RT5677_PWR_DSP_ST:
    case RT5677_PRIV_DATA:
    case RT5677_ASRC_22:
    --
    2.20.1


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