Messages in this thread | | | Subject | Re: [PATCH v3 4/4] phy: qcom-qmp: Add SW reset register | From | Manu Gautam <> | Date | Tue, 24 Dec 2019 09:10:35 +0530 |
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On 12/23/2019 8:00 PM, Vinod Koul wrote: > For V4 QMP UFS Phy, we need to assert reset bits, configure the phy and > then deassert it, so add the QPHY_SW_RESET register which does this. > > Signed-off-by: Vinod Koul <vkoul@kernel.org> > --- > drivers/phy/qualcomm/phy-qcom-qmp.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c > index ce5e18f188c3..7db2a94f7a99 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp.c > +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c > @@ -168,6 +168,7 @@ static const unsigned int sdm845_ufsphy_regs_layout[] = { > static const unsigned int sm8150_ufsphy_regs_layout[] = { > [QPHY_START_CTRL] = QPHY_V4_PHY_START, > [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_READY_STATUS, > + [QPHY_SW_RESET] = QPHY_V4_SW_RESET, > }; > > static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
Reviewed-by: Manu Gautam <mgautam@codeaurora.org>
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