Messages in this thread | | | Date | Wed, 11 Dec 2019 14:18:30 +0100 | From | Gerd Hoffmann <> | Subject | Re: [PATCH v2 1/2] drm/shmem: add support for per object caching attributes |
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Hi,
> btw on why udl does this: Imported bo are usually rendered by real hw, and > reading it uncached/wc is the more defensive setting. It would be kinda > nice if dma-buf would expose this, but I fear dma-api maintainers would > murder us if we even just propose that ... so it's a mess right now.
I suspect for imported dma-bufs we should leave the mmap() to the exporter instead of pulling the pages out of the sgt and map them ourself.
> btw the issue extends to dma access by devices too, e.g. both i915 and > amdgpu can select the coherency mode at runtime (using e.g. the pcie > no-snoop transaction mode), and we have similar uncoordinated hacks in > there too, like in udl.
Hmm. Ok. I guess I'm not going to try solve all that properly just for the little virtio fix.
Just curious: How do you tell your hardware? Are there bits for that in the gtt, simliar to the caching bits in the x86 page tables?
cheers, Gerd
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