Messages in this thread Patch in this message | | | Date | Fri, 01 Nov 2019 16:37:37 -0000 | From | "tip-bot2 for Tony Luck" <> | Subject | [tip: ras/core] x86/mce: Add Xeon Icelake to list of CPUs that support PPIN |
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The following commit has been merged into the ras/core branch of tip:
Commit-ID: dc6b025de95bcd22ff37c4fabb022ec8a027abf1 Gitweb: https://git.kernel.org/tip/dc6b025de95bcd22ff37c4fabb022ec8a027abf1 Author: Tony Luck <tony.luck@intel.com> AuthorDate: Mon, 28 Oct 2019 09:37:19 -07:00 Committer: Borislav Petkov <bp@suse.de> CommitterDate: Fri, 01 Nov 2019 17:29:36 +01:00
x86/mce: Add Xeon Icelake to list of CPUs that support PPIN
New CPU model, same MSRs to control and read the inventory number.
Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: linux-edac <linux-edac@vger.kernel.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: x86-ml <x86@kernel.org> Link: https://lkml.kernel.org/r/20191028163719.19708-1-tony.luck@intel.com --- arch/x86/kernel/cpu/mce/intel.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c index 68a1d25..e270d07 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -484,6 +484,7 @@ static void intel_ppin_init(struct cpuinfo_x86 *c) case INTEL_FAM6_BROADWELL_D: case INTEL_FAM6_BROADWELL_X: case INTEL_FAM6_SKYLAKE_X: + case INTEL_FAM6_ICELAKE_X: case INTEL_FAM6_XEON_PHI_KNL: case INTEL_FAM6_XEON_PHI_KNM:
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