Messages in this thread | | | Subject | Re: [PATCH v2 07/23] soc: fsl: qe: merge qe_ic.h into qe_ic.c | From | Christophe Leroy <> | Date | Wed, 30 Oct 2019 11:24:09 +0100 |
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Le 25/10/2019 à 14:40, Rasmus Villemoes a écrit : > The local qe_ic.h header is only used by qe_ic.c, so merge its > contents into the .c file. This is preparation for moving the driver > to drivers/irqchip/. It also avoids confusion between this header and > the one at include/soc/fsl/qe/qe_ic.h, which is included from a number > of places (qe_ic.c among others). > > Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk> > --- > drivers/soc/fsl/qe/qe_ic.c | 91 ++++++++++++++++++++++++++++++- > drivers/soc/fsl/qe/qe_ic.h | 108 ------------------------------------- > 2 files changed, 90 insertions(+), 109 deletions(-) > delete mode 100644 drivers/soc/fsl/qe/qe_ic.h > > diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c > index d420492b4c23..7b1870d2866a 100644 > --- a/drivers/soc/fsl/qe/qe_ic.c > +++ b/drivers/soc/fsl/qe/qe_ic.c > @@ -26,7 +26,96 @@ > #include <asm/io.h> > #include <soc/fsl/qe/qe_ic.h> > > -#include "qe_ic.h" > +#define NR_QE_IC_INTS 64 > + > +/* QE IC registers offset */ > +#define QEIC_CICR 0x00 > +#define QEIC_CIVEC 0x04 > +#define QEIC_CRIPNR 0x08 > +#define QEIC_CIPNR 0x0c > +#define QEIC_CIPXCC 0x10 > +#define QEIC_CIPYCC 0x14 > +#define QEIC_CIPWCC 0x18 > +#define QEIC_CIPZCC 0x1c > +#define QEIC_CIMR 0x20 > +#define QEIC_CRIMR 0x24 > +#define QEIC_CICNR 0x28 > +#define QEIC_CIPRTA 0x30 > +#define QEIC_CIPRTB 0x34 > +#define QEIC_CRICR 0x3c > +#define QEIC_CHIVEC 0x60 > + > +/* Interrupt priority registers */ > +#define CIPCC_SHIFT_PRI0 29 > +#define CIPCC_SHIFT_PRI1 26 > +#define CIPCC_SHIFT_PRI2 23 > +#define CIPCC_SHIFT_PRI3 20 > +#define CIPCC_SHIFT_PRI4 13 > +#define CIPCC_SHIFT_PRI5 10 > +#define CIPCC_SHIFT_PRI6 7 > +#define CIPCC_SHIFT_PRI7 4
I think you should drop all unused consts and only keep the ones that are used.
> + > +/* CICR priority modes */ > +#define CICR_GWCC 0x00040000 > +#define CICR_GXCC 0x00020000 > +#define CICR_GYCC 0x00010000 > +#define CICR_GZCC 0x00080000 > +#define CICR_GRTA 0x00200000 > +#define CICR_GRTB 0x00400000 > +#define CICR_HPIT_SHIFT 8 > +#define CICR_HPIT_MASK 0x00000300 > +#define CICR_HP_SHIFT 24 > +#define CICR_HP_MASK 0x3f000000 > + > +/* CICNR */ > +#define CICNR_WCC1T_SHIFT 20 > +#define CICNR_ZCC1T_SHIFT 28 > +#define CICNR_YCC1T_SHIFT 12 > +#define CICNR_XCC1T_SHIFT 4
Same here
> + > +/* CRICR */ > +#define CRICR_RTA1T_SHIFT 20 > +#define CRICR_RTB1T_SHIFT 28
Same
> + > +/* Signal indicator */ > +#define SIGNAL_MASK 3 > +#define SIGNAL_HIGH 2 > +#define SIGNAL_LOW 0
Only SIGNAL_HIGH seems to be used.
Christophe
> + > +struct qe_ic { > + /* Control registers offset */ > + u32 __iomem *regs; > + > + /* The remapper for this QEIC */ > + struct irq_domain *irqhost; > + > + /* The "linux" controller struct */ > + struct irq_chip hc_irq; > + > + /* VIRQ numbers of QE high/low irqs */ > + unsigned int virq_high; > + unsigned int virq_low; > +}; > + > +/* > + * QE interrupt controller internal structure > + */ > +struct qe_ic_info { > + /* Location of this source at the QIMR register */ > + u32 mask; > + > + /* Mask register offset */ > + u32 mask_reg; > + > + /* > + * For grouped interrupts sources - the interrupt code as > + * appears at the group priority register > + */ > + u8 pri_code; > + > + /* Group priority register offset */ > + u32 pri_reg; > +}; > > static DEFINE_RAW_SPINLOCK(qe_ic_lock); > > diff --git a/drivers/soc/fsl/qe/qe_ic.h b/drivers/soc/fsl/qe/qe_ic.h > deleted file mode 100644 > index 29b4d768e4a8..000000000000 > --- a/drivers/soc/fsl/qe/qe_ic.h > +++ /dev/null > @@ -1,108 +0,0 @@ > -/* SPDX-License-Identifier: GPL-2.0-or-later */ > -/* > - * drivers/soc/fsl/qe/qe_ic.h > - * > - * QUICC ENGINE Interrupt Controller Header > - * > - * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved. > - * > - * Author: Li Yang <leoli@freescale.com> > - * Based on code from Shlomi Gridish <gridish@freescale.com> > - */ > -#ifndef _POWERPC_SYSDEV_QE_IC_H > -#define _POWERPC_SYSDEV_QE_IC_H > - > -#include <soc/fsl/qe/qe_ic.h> > - > -#define NR_QE_IC_INTS 64 > - > -/* QE IC registers offset */ > -#define QEIC_CICR 0x00 > -#define QEIC_CIVEC 0x04 > -#define QEIC_CRIPNR 0x08 > -#define QEIC_CIPNR 0x0c > -#define QEIC_CIPXCC 0x10 > -#define QEIC_CIPYCC 0x14 > -#define QEIC_CIPWCC 0x18 > -#define QEIC_CIPZCC 0x1c > -#define QEIC_CIMR 0x20 > -#define QEIC_CRIMR 0x24 > -#define QEIC_CICNR 0x28 > -#define QEIC_CIPRTA 0x30 > -#define QEIC_CIPRTB 0x34 > -#define QEIC_CRICR 0x3c > -#define QEIC_CHIVEC 0x60 > - > -/* Interrupt priority registers */ > -#define CIPCC_SHIFT_PRI0 29 > -#define CIPCC_SHIFT_PRI1 26 > -#define CIPCC_SHIFT_PRI2 23 > -#define CIPCC_SHIFT_PRI3 20 > -#define CIPCC_SHIFT_PRI4 13 > -#define CIPCC_SHIFT_PRI5 10 > -#define CIPCC_SHIFT_PRI6 7 > -#define CIPCC_SHIFT_PRI7 4 > - > -/* CICR priority modes */ > -#define CICR_GWCC 0x00040000 > -#define CICR_GXCC 0x00020000 > -#define CICR_GYCC 0x00010000 > -#define CICR_GZCC 0x00080000 > -#define CICR_GRTA 0x00200000 > -#define CICR_GRTB 0x00400000 > -#define CICR_HPIT_SHIFT 8 > -#define CICR_HPIT_MASK 0x00000300 > -#define CICR_HP_SHIFT 24 > -#define CICR_HP_MASK 0x3f000000 > - > -/* CICNR */ > -#define CICNR_WCC1T_SHIFT 20 > -#define CICNR_ZCC1T_SHIFT 28 > -#define CICNR_YCC1T_SHIFT 12 > -#define CICNR_XCC1T_SHIFT 4 > - > -/* CRICR */ > -#define CRICR_RTA1T_SHIFT 20 > -#define CRICR_RTB1T_SHIFT 28 > - > -/* Signal indicator */ > -#define SIGNAL_MASK 3 > -#define SIGNAL_HIGH 2 > -#define SIGNAL_LOW 0 > - > -struct qe_ic { > - /* Control registers offset */ > - u32 __iomem *regs; > - > - /* The remapper for this QEIC */ > - struct irq_domain *irqhost; > - > - /* The "linux" controller struct */ > - struct irq_chip hc_irq; > - > - /* VIRQ numbers of QE high/low irqs */ > - unsigned int virq_high; > - unsigned int virq_low; > -}; > - > -/* > - * QE interrupt controller internal structure > - */ > -struct qe_ic_info { > - /* Location of this source at the QIMR register */ > - u32 mask; > - > - /* Mask register offset */ > - u32 mask_reg; > - > - /* > - * For grouped interrupts sources - the interrupt code as > - * appears at the group priority register > - */ > - u8 pri_code; > - > - /* Group priority register offset */ > - u32 pri_reg; > -}; > - > -#endif /* _POWERPC_SYSDEV_QE_IC_H */ >
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