Messages in this thread | | | Subject | Re: Fwd: Re: [PATCH v3 1/2] dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller | From | Dilip Kota <> | Date | Thu, 3 Oct 2019 14:35:02 +0800 |
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Hi Rob,
On 18/9/2019 2:56 PM, Dilip Kota wrote: > On 9/18/2019 2:40 AM, Rob Herring wrote: >> On Wed, Sep 04, 2019 at 06:10:30PM +0800, Dilip Kota wrote: >>> The Intel PCIe RC controller is Synopsys Designware >>> based PCIe core. Add YAML schemas for PCIe in RC mode >>> present in Intel Universal Gateway soc. >>> >>> Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com> >>> --- >>> changes on v3: >>> Add the appropriate License-Identifier >>> Rename intel,rst-interval to 'reset-assert-us' >>> Add additionalProperties: false >>> Rename phy-names to 'pciephy' >>> Remove the dtsi node split of SoC and board in the example >>> Add #interrupt-cells = <1>; or else interrupt parsing will fail >>> Name yaml file with compatible name >>> >>> .../devicetree/bindings/pci/intel,lgm-pcie.yaml | 137 >>> +++++++++++++++++++++ >>> 1 file changed, 137 insertions(+) >>> create mode 100644 >>> Documentation/devicetree/bindings/pci/intel,lgm-pcie.yaml >>> >>> diff --git >>> a/Documentation/devicetree/bindings/pci/intel,lgm-pcie.yaml >>> b/Documentation/devicetree/bindings/pci/intel,lgm-pcie.yaml >>> new file mode 100644 >>> index 000000000000..5e5cc7fd66cd >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/pci/intel,lgm-pcie.yaml >>> @@ -0,0 +1,137 @@ >>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/pci/intel-pcie.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Intel AXI bus based PCI express root complex >>> + >>> +maintainers: >>> + - Dilip Kota <eswara.kota@linux.intel.com> >>> + >>> +properties: >>> + compatible: >>> + const: intel,lgm-pcie >>> + >>> + device_type: >>> + const: pci >>> + >>> + "#address-cells": >>> + const: 3 >>> + >>> + "#size-cells": >>> + const: 2 >> These all belong in a common schema. >> >>> + >>> + reg: >>> + items: >>> + - description: Controller control and status registers. >>> + - description: PCIe configuration registers. >>> + - description: Controller application registers. >>> + >>> + reg-names: >>> + items: >>> + - const: dbi >>> + - const: config >>> + - const: app >>> + >>> + ranges: >>> + description: Ranges for the PCI memory and I/O regions. >> And this. >> >>> + >>> + resets: >>> + maxItems: 1 >>> + >>> + clocks: >>> + description: PCIe registers interface clock. >>> + >>> + phys: >>> + maxItems: 1 >>> + >>> + phy-names: >>> + const: pciephy >>> + >>> + reset-gpios: >>> + maxItems: 1 >>> + >>> + num-lanes: >>> + description: Number of lanes to use for this port. >>> + >>> + linux,pci-domain: >>> + $ref: /schemas/types.yaml#/definitions/uint32 >>> + description: PCI domain ID. >> These 2 also should be common. >> >>> + >>> + interrupts: >>> + description: PCIe core integrated miscellaneous interrupt. >> How many? No need for description if there's only 1. >> >>> + >>> + '#interrupt-cells': >>> + const: 1 >>> + >>> + interrupt-map-mask: >>> + description: Standard PCI IRQ mapping properties. >>> + >>> + interrupt-map: >>> + description: Standard PCI IRQ mapping properties. >>> + >>> + max-link-speed: >>> + description: Specify PCI Gen for link capability. >>> + >>> + bus-range: >>> + description: Range of bus numbers associated with this controller. >> All common. > You mean to remove all the common schema entries description!. > In most of the Documention/devicetree/binding/pci documents all the > common entries are described so I followed the same.
If common schemas are removed, getting below warning during the dt_binding_check.
Documentation/devicetree/bindings/pci/intel,lgm-pcie.example.dt.yaml: pcie@d0e00000: '#address-cells', '#interrupt-cells', '#size-cells', 'bus-range', 'device_type', 'interrupt-map', 'interrupt-map-mask', 'interrupt-parent', 'linux,pci-domain', 'ranges', 'reset-gpios' do not match any of the regexes: 'pinctrl-[0-9]+'
Regards, Dilip
>> >>> + >>> + reset-assert-ms: >>> + description: | >>> + Device reset interval in ms. >>> + Some devices need an interval upto 500ms. By default it is 100ms. >> This is a property of a device, so it belongs in a device node. How >> would you deal with this without DT? > This property is for the PCIe RC to keep a delay before notifying the > reset to the device. > If this entry is not present, PCIe driver will set a default value of > 100ms. >> >>> + >>> +required: >>> + - compatible >>> + - device_type >>> + - reg >>> + - reg-names >>> + - ranges >>> + - resets >>> + - clocks >>> + - phys >>> + - phy-names >>> + - reset-gpios >>> + - num-lanes >>> + - linux,pci-domain >>> + - interrupts >>> + - interrupt-map >>> + - interrupt-map-mask >>> + >>> +additionalProperties: false >>> + >>> +examples: >>> + - | >>> + pcie10:pcie@d0e00000 { >>> + compatible = "intel,lgm-pcie"; >>> + device_type = "pci"; >>> + #address-cells = <3>; >>> + #size-cells = <2>; >>> + reg = < >>> + 0xd0e00000 0x1000 >>> + 0xd2000000 0x800000 >>> + 0xd0a41000 0x1000 >>> + >; >>> + reg-names = "dbi", "config", "app"; >>> + linux,pci-domain = <0>; >>> + max-link-speed = <4>; >>> + bus-range = <0x00 0x08>; >>> + interrupt-parent = <&ioapic1>; >>> + interrupts = <67 1>; >>> + #interrupt-cells = <1>; >>> + interrupt-map-mask = <0 0 0 0x7>; >>> + interrupt-map = <0 0 0 1 &ioapic1 27 1>, >>> + <0 0 0 2 &ioapic1 28 1>, >>> + <0 0 0 3 &ioapic1 29 1>, >>> + <0 0 0 4 &ioapic1 30 1>; >>> + ranges = <0x02000000 0 0xd4000000 0xd4000000 0 0x04000000>; >>> + resets = <&rcu0 0x50 0>; >>> + clocks = <&cgu0 LGM_GCLK_PCIE10>; >>> + phys = <&cb0phy0>; >>> + phy-names = "pciephy"; >>> + status = "okay"; >>> + reset-assert-ms = <500>; >>> + reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; >>> + num-lanes = <2>; >>> + }; >>> -- 2.11.0 >>>
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