Messages in this thread | | | Date | Tue, 29 Oct 2019 08:43:21 +0100 | From | Maxime Ripard <> | Subject | Re: [PATCH] clk: sunxi-ng: a80: fix the zero'ing of bits 16 and 18 |
| |
On Wed, Oct 23, 2019 at 12:28:09PM +0100, Colin King wrote: > From: Colin Ian King <colin.king@canonical.com> > > The zero'ing of bits 16 and 18 is incorrect. Currently the code > is masking with the bitwise-and of BIT(16) & BIT(18) which is > 0, so the updated value for val is always zero. Fix this by bitwise > and-ing value with the correct mask that will zero bits 16 and 18. > > Addresses-Coverity: (" Suspicious &= or |= constant expression") > Fixes: b8eb71dcdd08 ("clk: sunxi-ng: Add A80 CCU") > Signed-off-by: Colin Ian King <colin.king@canonical.com>
Applied, thanks! Maxime [unhandled content-type:application/pgp-signature] | |