Messages in this thread | | | Date | Mon, 28 Oct 2019 15:44:20 +0000 | From | Will Deacon <> | Subject | Re: [PATCH] iommu/dma: Add support for DMA_ATTR_SYS_CACHE |
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On Mon, Oct 28, 2019 at 12:37:28PM +0100, Christoph Hellwig wrote: > On Mon, Oct 28, 2019 at 11:24:58AM +0000, Will Deacon wrote: > > Agreed. The way I /think/ it works is that on many SoCs there is a > > system/last-level cache (LLC) which effectively sits in front of memory for > > all masters. Even if a device isn't coherent with the CPU caches, we still > > want to be able to allocate into the LLC. Why this doesn't happen > > automatically is beyond me, but it appears that on these Qualcomm designs > > you actually have to set the memory attributes up in the page-table to > > ensure that the resulting memory transactions are non-cacheable for the CPU > > but cacheable for the LLC. Without any changes, the transactions are > > non-cacheable in both of them which assumedly has a performance cost. > > > > But you can see that I'm piecing things together myself here. Isaac? > > If that is the case it sounds like we'd want to drive this through > DT properties, not the driver API. But again, without an actual consumer > it pretty much is a moot point anyway.
I think there's certainly a DT aspect to it so that the driver knows that the SoC is hooked up this way, but I agree that we need a consumer so that we can figure out how dynamic this needs to be. If it's just a fire-and-forget thing then it needn't escape the IOMMU layer, but I fear that it's probably more flexible than that.
If nothing shows up for 5.6, I'll send a patch to remove it (since Jordan said there was something coming soon [1])
Will
[1] http://lkml.kernel.org/r/20191024153832.GA7966@jcrouse1-lnx.qualcomm.com
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