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    SubjectRE: [PATCH v7 10/11] iommu/vt-d: Support flushing more translation cache types
    Date
    > From: Jacob Pan [mailto:jacob.jun.pan@linux.intel.com]
    > Sent: Friday, October 25, 2019 3:55 AM
    >
    > When Shared Virtual Memory is exposed to a guest via vIOMMU, scalable
    > IOTLB invalidation may be passed down from outside IOMMU subsystems.

    from outside of host IOMMU subsystem

    > This patch adds invalidation functions that can be used for additional
    > translation cache types.
    >
    > Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
    > ---
    > drivers/iommu/dmar.c | 46
    > +++++++++++++++++++++++++++++++++++++++++++++
    > drivers/iommu/intel-pasid.c | 3 ++-
    > include/linux/intel-iommu.h | 21 +++++++++++++++++----
    > 3 files changed, 65 insertions(+), 5 deletions(-)
    >
    > diff --git a/drivers/iommu/dmar.c b/drivers/iommu/dmar.c
    > index 49bb7d76e646..0ce2d32ff99e 100644
    > --- a/drivers/iommu/dmar.c
    > +++ b/drivers/iommu/dmar.c
    > @@ -1346,6 +1346,20 @@ void qi_flush_iotlb(struct intel_iommu *iommu,
    > u16 did, u64 addr,
    > qi_submit_sync(&desc, iommu);
    > }
    >
    > +/* PASID-based IOTLB Invalidate */
    > +void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u64 addr, u32
    > pasid,

    qi_flush_iotlb_pasid.

    > + unsigned int size_order, u64 granu, int ih)
    > +{
    > + struct qi_desc desc = {.qw2 = 0, .qw3 = 0};
    > +
    > + desc.qw0 = QI_EIOTLB_PASID(pasid) | QI_EIOTLB_DID(did) |
    > + QI_EIOTLB_GRAN(granu) | QI_EIOTLB_TYPE;
    > + desc.qw1 = QI_EIOTLB_ADDR(addr) | QI_EIOTLB_IH(ih) |
    > + QI_EIOTLB_AM(size_order);
    > +
    > + qi_submit_sync(&desc, iommu);
    > +}
    > +
    > void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
    > u16 qdep, u64 addr, unsigned mask)
    > {
    > @@ -1369,6 +1383,38 @@ void qi_flush_dev_iotlb(struct intel_iommu
    > *iommu, u16 sid, u16 pfsid,
    > qi_submit_sync(&desc, iommu);
    > }
    >
    > +/* PASID-based device IOTLB Invalidate */
    > +void qi_flush_dev_piotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
    > + u32 pasid, u16 qdep, u64 addr, unsigned size_order, u64
    > granu)
    > +{
    > + struct qi_desc desc;
    > +
    > + desc.qw0 = QI_DEV_EIOTLB_PASID(pasid) | QI_DEV_EIOTLB_SID(sid)
    > |
    > + QI_DEV_EIOTLB_QDEP(qdep) | QI_DEIOTLB_TYPE |
    > + QI_DEV_IOTLB_PFSID(pfsid);
    > + desc.qw1 = QI_DEV_EIOTLB_GLOB(granu);
    > +
    > + /* If S bit is 0, we only flush a single page. If S bit is set,
    > + * The least significant zero bit indicates the invalidation address
    > + * range. VT-d spec 6.5.2.6.
    > + * e.g. address bit 12[0] indicates 8KB, 13[0] indicates 16KB.
    > + */
    > + if (!size_order) {
    > + desc.qw0 |= QI_DEV_EIOTLB_ADDR(addr) &
    > ~QI_DEV_EIOTLB_SIZE;
    > + } else {
    > + unsigned long mask = 1UL << (VTD_PAGE_SHIFT +
    > size_order);
    > + desc.qw1 |= QI_DEV_EIOTLB_ADDR(addr & ~mask) |
    > QI_DEV_EIOTLB_SIZE;
    > + }
    > + qi_submit_sync(&desc, iommu);
    > +}
    > +
    > +void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, u64
    > granu, int pasid)
    > +{
    > + struct qi_desc desc = {.qw1 = 0, .qw2 = 0, .qw3 = 0};
    > +
    > + desc.qw0 = QI_PC_PASID(pasid) | QI_PC_DID(did) |
    > QI_PC_GRAN(granu) | QI_PC_TYPE;
    > + qi_submit_sync(&desc, iommu);
    > +}
    > /*
    > * Disable Queued Invalidation interface.
    > */
    > diff --git a/drivers/iommu/intel-pasid.c b/drivers/iommu/intel-pasid.c
    > index f846a907cfcf..6d7a701ef4d3 100644
    > --- a/drivers/iommu/intel-pasid.c
    > +++ b/drivers/iommu/intel-pasid.c
    > @@ -491,7 +491,8 @@ pasid_cache_invalidation_with_pasid(struct
    > intel_iommu *iommu,
    > {
    > struct qi_desc desc;
    >
    > - desc.qw0 = QI_PC_DID(did) | QI_PC_PASID_SEL |
    > QI_PC_PASID(pasid);
    > + desc.qw0 = QI_PC_DID(did) | QI_PC_GRAN(QI_PC_PASID_SEL) |
    > + QI_PC_PASID(pasid) | QI_PC_TYPE;
    > desc.qw1 = 0;
    > desc.qw2 = 0;
    > desc.qw3 = 0;
    > diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
    > index 6c74c71b1ebf..a25fb3a0ea5b 100644
    > --- a/include/linux/intel-iommu.h
    > +++ b/include/linux/intel-iommu.h
    > @@ -332,7 +332,7 @@ enum {
    > #define QI_IOTLB_GRAN(gran) (((u64)gran) >>
    > (DMA_TLB_FLUSH_GRANU_OFFSET-4))
    > #define QI_IOTLB_ADDR(addr) (((u64)addr) & VTD_PAGE_MASK)
    > #define QI_IOTLB_IH(ih) (((u64)ih) << 6)
    > -#define QI_IOTLB_AM(am) (((u8)am))
    > +#define QI_IOTLB_AM(am) (((u8)am) & 0x3f)
    >
    > #define QI_CC_FM(fm) (((u64)fm) << 48)
    > #define QI_CC_SID(sid) (((u64)sid) << 32)
    > @@ -350,16 +350,21 @@ enum {
    > #define QI_PC_DID(did) (((u64)did) << 16)
    > #define QI_PC_GRAN(gran) (((u64)gran) << 4)
    >
    > -#define QI_PC_ALL_PASIDS (QI_PC_TYPE | QI_PC_GRAN(0))
    > -#define QI_PC_PASID_SEL (QI_PC_TYPE | QI_PC_GRAN(1))
    > +/* PASID cache invalidation granu */
    > +#define QI_PC_ALL_PASIDS 0
    > +#define QI_PC_PASID_SEL 1
    >
    > #define QI_EIOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
    > #define QI_EIOTLB_IH(ih) (((u64)ih) << 6)
    > -#define QI_EIOTLB_AM(am) (((u64)am))
    > +#define QI_EIOTLB_AM(am) (((u64)am) & 0x3f)
    > #define QI_EIOTLB_PASID(pasid) (((u64)pasid) << 32)
    > #define QI_EIOTLB_DID(did) (((u64)did) << 16)
    > #define QI_EIOTLB_GRAN(gran) (((u64)gran) << 4)
    >
    > +/* QI Dev-IOTLB inv granu */
    > +#define QI_DEV_IOTLB_GRAN_ALL 1
    > +#define QI_DEV_IOTLB_GRAN_PASID_SEL 0
    > +
    > #define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK)
    > #define QI_DEV_EIOTLB_SIZE (((u64)1) << 11)
    > #define QI_DEV_EIOTLB_GLOB(g) ((u64)g)
    > @@ -655,8 +660,16 @@ extern void qi_flush_context(struct intel_iommu
    > *iommu, u16 did, u16 sid,
    > u8 fm, u64 type);
    > extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
    > unsigned int size_order, u64 type);
    > +extern void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u64 addr,
    > + u32 pasid, unsigned int size_order, u64 type, int ih);
    > extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16
    > pfsid,
    > u16 qdep, u64 addr, unsigned mask);
    > +
    > +extern void qi_flush_dev_piotlb(struct intel_iommu *iommu, u16 sid, u16
    > pfsid,
    > + u32 pasid, u16 qdep, u64 addr, unsigned size_order,
    > u64 granu);
    > +
    > +extern void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did,
    > u64 granu, int pasid);
    > +
    > extern int qi_submit_sync(struct qi_desc *desc, struct intel_iommu
    > *iommu);
    >
    > extern int dmar_ir_support(void);
    > --
    > 2.7.4

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