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SubjectRE: [PATCH v4 0/3] PCI: Add Intel PCIe Driver and respective dt-binding yaml file
Date
Hi,


On Mon, Oct 21, 2019 at 7:39:17, Dilip Kota <eswara.kota@linux.intel.com>
wrote:

> Intel PCIe is synopsys based controller utilizes the Designware

Please do this general replacement in all your patches.

s/synopsys/Synopsys

and

s/Designware/DesignWare

> framework for host initialization and intel application
> specific register configurations.
>
> Changes on v4:
> Add lane resizing API in PCIe DesignWare driver.
> Intel PCIe driver uses it for lane resizing which
> is being exposed through sysfs attributes.
> Add Intel PCIe sysfs attributes is in separate patch.
> Address review comments given on v3.
>
> Changes on v3:
> Compared to v2, map_irq() patch is removed as it is no longer
> required for Intel PCIe driver. Intel PCIe driver does platform
> specific interrupt configuration during core initialization. So
> changed the subject line too.
> Address v2 review comments for DT binding and PCIe driver
>
> Dilip Kota (3):
> dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller
> dwc: PCI: intel: PCIe RC controller driver
> pci: intel: Add sysfs attributes to configure pcie link
>
> .../devicetree/bindings/pci/intel-gw-pcie.yaml | 135 ++++
> drivers/pci/controller/dwc/Kconfig | 10 +
> drivers/pci/controller/dwc/Makefile | 1 +
> drivers/pci/controller/dwc/pcie-designware.c | 43 ++
> drivers/pci/controller/dwc/pcie-designware.h | 15 +
> drivers/pci/controller/dwc/pcie-intel-gw.c | 700 +++++++++++++++
> include/uapi/linux/pci_regs.h | 1 +
> 7 files changed, 905 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
> create mode 100644 drivers/pci/controller/dwc/pcie-intel-gw.c
>
> --
> 2.11.0


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