lkml.org 
[lkml]   [2019]   [Oct]   [10]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH 4.19 096/114] arm64: Always enable ssb vulnerability detection
    Date
    From: Jeremy Linton <jeremy.linton@arm.com>

    [ Upstream commit d42281b6e49510f078ace15a8ea10f71e6262581 ]

    Ensure we are always able to detect whether or not the CPU is affected
    by SSB, so that we can later advertise this to userspace.

    Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
    Reviewed-by: Andre Przywara <andre.przywara@arm.com>
    Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
    Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
    [will: Use IS_ENABLED instead of #ifdef]
    Signed-off-by: Will Deacon <will.deacon@arm.com>
    Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    arch/arm64/include/asm/cpufeature.h | 4 ----
    arch/arm64/kernel/cpu_errata.c | 9 +++++----
    2 files changed, 5 insertions(+), 8 deletions(-)

    --- a/arch/arm64/include/asm/cpufeature.h
    +++ b/arch/arm64/include/asm/cpufeature.h
    @@ -525,11 +525,7 @@ static inline int arm64_get_ssbd_state(v
    #endif
    }

    -#ifdef CONFIG_ARM64_SSBD
    void arm64_set_ssbd_mitigation(bool state);
    -#else
    -static inline void arm64_set_ssbd_mitigation(bool state) {}
    -#endif

    #endif /* __ASSEMBLY__ */

    --- a/arch/arm64/kernel/cpu_errata.c
    +++ b/arch/arm64/kernel/cpu_errata.c
    @@ -239,7 +239,6 @@ enable_smccc_arch_workaround_1(const str
    }
    #endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */

    -#ifdef CONFIG_ARM64_SSBD
    DEFINE_PER_CPU_READ_MOSTLY(u64, arm64_ssbd_callback_required);

    int ssbd_state __read_mostly = ARM64_SSBD_KERNEL;
    @@ -312,6 +311,11 @@ void __init arm64_enable_wa2_handling(st

    void arm64_set_ssbd_mitigation(bool state)
    {
    + if (!IS_ENABLED(CONFIG_ARM64_SSBD)) {
    + pr_info_once("SSBD disabled by kernel configuration\n");
    + return;
    + }
    +
    if (this_cpu_has_cap(ARM64_SSBS)) {
    if (state)
    asm volatile(SET_PSTATE_SSBS(0));
    @@ -431,7 +435,6 @@ out_printmsg:

    return required;
    }
    -#endif /* CONFIG_ARM64_SSBD */

    #ifdef CONFIG_ARM64_ERRATUM_1463225
    DEFINE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa);
    @@ -710,14 +713,12 @@ const struct arm64_cpu_capabilities arm6
    ERRATA_MIDR_RANGE_LIST(arm64_harden_el2_vectors),
    },
    #endif
    -#ifdef CONFIG_ARM64_SSBD
    {
    .desc = "Speculative Store Bypass Disable",
    .capability = ARM64_SSBD,
    .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
    .matches = has_ssbd_mitigation,
    },
    -#endif
    #ifdef CONFIG_ARM64_ERRATUM_1463225
    {
    .desc = "ARM erratum 1463225",

    \
     
     \ /
      Last update: 2019-10-10 10:49    [W:4.140 / U:0.076 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site