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    SubjectRe: [PATCH v2 5/7] KVM:VMX: Pass through host CET related MSRs to Guest.
    On Wed, Jan 23, 2019 at 04:59:07AM +0800, Yang Weijiang wrote:
    > The CET runtime settings, i.e., CET state control bits(IA32_U_CET/
    > IA32_S_CET), CET SSP(IA32_PL3_SSP/IA32_PL0_SSP) and SSP table address
    > (IA32_INTERRUPT_SSP_TABLE_ADDR) are task/thread specific, therefore,
    > OS needs to save/restore the states properly during context switch,
    > e.g., task/thread switching, interrupt/exception handling, it uses
    > xsaves/xrstors to achieve that.
    >
    > The difference between VMCS CET area fields and xsave CET area, is that
    > the former is for state retention during Guest/Host context
    > switch while the latter is for state retention during OS execution.
    >
    > Linux currently doesn't support CPL1 and CPL2, so SSPs for these level
    > are skipped here.
    >
    > Signed-off-by: Zhang Yi Z <yi.z.zhang@linux.intel.com>
    > Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
    > ---
    > arch/x86/kvm/vmx.c | 16 ++++++++++++++++
    > 1 file changed, 16 insertions(+)
    >
    > diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
    > index 7bbb8b26e901..68c0e5e41cb1 100644
    > --- a/arch/x86/kvm/vmx.c
    > +++ b/arch/x86/kvm/vmx.c
    > @@ -11531,6 +11531,7 @@ static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
    > vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
    > vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
    > vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
    > +

    Spurious whitespace change.

    > vmx->msr_bitmap_mode = 0;
    >
    > vmx->loaded_vmcs = &vmx->vmcs01;
    > @@ -11769,6 +11770,8 @@ static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
    > static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
    > {
    > struct vcpu_vmx *vmx = to_vmx(vcpu);
    > + struct kvm_cpuid_entry2 *best;
    > + unsigned long *msr_bitmap;
    >
    > if (cpu_has_secondary_exec_ctrls()) {
    > vmx_compute_secondary_exec_control(vmx);
    > @@ -11786,6 +11789,19 @@ static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
    > nested_vmx_cr_fixed1_bits_update(vcpu);
    > nested_vmx_entry_exit_ctls_update(vcpu);
    > }
    > +
    > + msr_bitmap = vmx->vmcs01.msr_bitmap;
    > + best = kvm_find_cpuid_entry(vcpu, 7, 0);
    > + if ((best && best->function == 0x7) &&
    > + ((best->ecx & bit(X86_FEATURE_SHSTK)) |
    > + (best->edx & bit(X86_FEATURE_IBT)))) {
    > + vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_U_CET, MSR_TYPE_RW);
    > + vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_S_CET, MSR_TYPE_RW);
    > + vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_INT_SSP_TAB, MSR_TYPE_RW);
    > + vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_PL0_SSP, MSR_TYPE_RW);
    > + vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_PL3_SSP, MSR_TYPE_RW);

    kvm_cpuid_update() an be called multiple times, don't we need to look
    for a change in status as opposed to the bits being enabled? And at
    that point toggling interception should probably be wrapped in a helper
    function.

    > + }
    > +
    > }
    >
    > static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
    > --
    > 2.17.1
    >

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