Messages in this thread Patch in this message | | | Date | Fri, 25 Jan 2019 18:08:14 +0000 | From | Catalin Marinas <> | Subject | Re: [PATCH v2 1/1] arm64: Add workaround for Fujitsu A64FX erratum 010001 |
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On Tue, Jan 22, 2019 at 08:54:33AM +0000, Zhang, Lei wrote: > diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c > index efb7b2c..37e4f18 100644 > --- a/arch/arm64/mm/fault.c > +++ b/arch/arm64/mm/fault.c > @@ -666,6 +666,28 @@ static int do_sea(unsigned long addr, unsigned int esr, struct pt_regs *regs) > return 0; > } > > +static int do_bad_unknown_63(unsigned long addr, unsigned int esr, struct pt_regs *regs) > +{ > + /* > + * On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), > + * memory accesses may spuriously trigger data aborts with > + * DFSC=0b111111. > + */ > + if (IS_ENABLED(CONFIG_FUJITSU_ERRATUM_010001)) { > + if (cpus_have_cap(ARM64_WORKAROUND_FUJITSU_A64FX_0100001)) { > + return 0; > + } else { /* cpu capabilities maybe not ready*/ > + unsigned int current_cpu_midr = read_cpuid_id(); > + const struct midr_range fujitsu_a64fx_midr_range = { > + MIDR_FUJITSU_A64FX, MIDR_CPU_VAR_REV(0, 0), MIDR_CPU_VAR_REV(1, 0) > + }; > + if (is_midr_in_range(current_cpu_midr, &fujitsu_a64fx_midr_range) == TRUE) > + return 0; > + } > + } > + return do_bad(addr, esr, regs); > +}
IIUC, this can happen very early when the errata framework isn't yet ready. Given that this is not on a fast path (you already took a fault), I don't think it's worth optimising for cpus_have_cap() (and ARM64_WORKAROUND_FUJITSU_A64FX_0100001). I've seen Mark's comments on why checking MIDR in a preemptible context is not a good idea but I suspect your platform is homogeneous (i.e. not big.LITTLE).
-- Catalin
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