Messages in this thread | | | From | Ard Biesheuvel <> | Date | Mon, 21 Jan 2019 18:59:10 +0100 | Subject | Re: [RFC PATCH] drm: disable WC optimization for cache coherent devices on non-x86 |
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On Mon, 21 Jan 2019 at 18:55, Michel Dänzer <michel@daenzer.net> wrote: > > On 2019-01-21 5:30 p.m., Ard Biesheuvel wrote: > > On Mon, 21 Jan 2019 at 17:22, Christoph Hellwig <hch@infradead.org> wrote: > > > >> Until that happens we should just change the driver ifdefs to default > >> the hacks to off and only enable them on setups where we 100% > >> positively know that they actually work. And document that fact > >> in big fat comments. > > > > Well, as I mentioned in my commit log as well, if we default to off > > unless CONFIG_X86, we may break working setups on MIPS and Power where > > the device is in fact non-cache coherent, and relies on this > > 'optimization' to get things working. > > FWIW, the amdgpu driver doesn't rely on non-snooped transfers for > correct basic operation (the scenario Christian brought up is a very > specialized use-case), so that shouldn't be an issue. >
The point is that this is only true for x86.
On other architectures, the use of non-cached mappings on the CPU side means that you /do/ rely on non-snooped transfers, since if those transfers turn out not to snoop inadvertently, the accesses are incoherent with the CPU's view of memory.
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