Messages in this thread | | | Date | Fri, 18 Jan 2019 11:15:14 -0300 | From | Paul Cercueil <> | Subject | Re: [PATCH 1/8] MIPS: DTS: CI20: Set BCH clock to 200 MHz |
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Hi,
On Fri, Jan 18, 2019 at 5:07 AM, Boris Brezillon <bbrezillon@kernel.org> wrote: > Hi Paul, > > On Thu, 17 Jan 2019 22:06:27 -0300 > Paul Cercueil <paul@crapouillou.net <mailto:paul@crapouillou.net>> > wrote: > >> This is currently done inside the jz4780-bch driver, but it really >> should be done here instead. >> > > I disagree with that statement. If it's a per-SoC constraint then you > can select the appropriate rate based on the compatible in the driver. > If the clock rate depends on the NAND chip it probably means it's used > to generate the RE/WE pulse and should depend on the NAND timings > passed to ->setup_data_interface(). In either case, this should not be > specified in the DT.
Alright, I'll drop the patch.
> Regards, > > Boris > >> Signed-off-by: Paul Cercueil <paul@crapouillou.net >> <mailto:paul@crapouillou.net>> >> --- >> arch/mips/boot/dts/ingenic/ci20.dts | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/arch/mips/boot/dts/ingenic/ci20.dts >> b/arch/mips/boot/dts/ingenic/ci20.dts >> index 50cff3cbcc6d..aa892ec54d0a 100644 >> --- a/arch/mips/boot/dts/ingenic/ci20.dts >> +++ b/arch/mips/boot/dts/ingenic/ci20.dts >> @@ -111,6 +111,9 @@ >> pinctrl-names = "default"; >> pinctrl-0 = <&pins_nemc>; >> >> + assigned-clocks = <&cgu JZ4780_CLK_BCH>; >> + assigned-clock-rates = <200000000>; >> + >> nand@1 { >> reg = <1>; >> >
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