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Subject[PATCH v5 0/4] PCIE support for i.MX8MQ

This series contains changes I made in order to enable support of PCIE
IP block on i.MX8MQ SoCs.

Changes since [v4]:

- Collected Reviewed-by from Lucas

- Replaced ((ARM || ARM64) && COMPILE_TEST) with COMPILE_TEST as per
suggestion from Rob

Changes since [v3]:

- Based on feedback from NXP, DIRECT_SPEED_CHANGE quirk was expanded
to cover both i.MX7 and i.MX8MQ

- Code setting device type in GPR12 moved to a standalone function

- Explicit "fsl,controller-id" binding was dropped, replaced by using
controller physical address to determine logical ID

- Dropped Reviewed-by from Lucas for patch 4/4 due to the change
above (haven't heard explicit "yea" for it from him)

Changes since [v2], [fixes]:

- Incorporated [patch] introducing drvdata

- i.MX6 PHY operation gating converted to a single patch and to use a
dedicated flag instead of doing explicit variant check

- Kconfig entry changed to use ARM64 && ARCH_MXC

- Dropped FALLTHROUGH annotations

Changes since [v1]:

- Driver changed to use single "fsl,controller-id" property to
distinguish between two intances of PCIE IP block

- All code pertaining to L1SS was dropped to simplify the patch

- Documented additions to DT bindings

Feedback is welcome!

Andrey Smirnov


Andrey Smirnov (4):
PCI: imx6: introduce drvdata
PCI: imx6: Mark PHY functions as i.MX6 specific
PCI: imx6: Convert DIRECT_SPEED_CHANGE quirk code to use a flag
PCI: imx6: Add support for i.MX8MQ

.../bindings/pci/fsl,imx6q-pcie.txt | 3 +-
drivers/pci/controller/dwc/Kconfig | 4 +-
drivers/pci/controller/dwc/pci-imx6.c | 150 +++++++++++++++---
3 files changed, 133 insertions(+), 24 deletions(-)


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