Messages in this thread | | | Date | Fri, 7 Sep 2018 21:54:11 +0200 (CEST) | From | Thomas Gleixner <> | Subject | Re: [PATCH v2 3/3] x86/pti/64: Remove the SYSCALL64 entry trampoline |
| |
On Wed, 5 Sep 2018, Andy Lutomirski wrote: > On Tue, Sep 4, 2018 at 12:04 AM, Peter Zijlstra <peterz@infradead.org> wrote: > > Can we have a few words on why this solution and not this alternative? I > > mean, you raise the possibility, but then surely you chose not to > > implement that. Might as well share that with us. > > I can give some pros and cons. With the other approach: > > - We avoid a pipeline stall.
Which is good.
> - We execute from an extra page and read from another extra page > during the syscall. (The latter is because we need to use a relative > addressing mode to find sp1 -- it's the same *cacheline* we'd use > anyway, but we're accessing it using an alias, so it's an extra TLB > entry.)
Ok, but is this really an issue with PTI?
> - We use more memory. This would be one page per CPU for a simple > implementation and 64-ish bytes per CPU or one page per node for a > more complex implementation.
That's the least interesting argument really.
> - More code complexity.
Ok, but how much complex code is that?
> I'm not convinced this is a good tradeoff.
Well, the real question here is whether this has any advantage vs. the percpu area exposure?
Thanks,
tglx
| |