Messages in this thread | | | Date | Wed, 5 Sep 2018 09:16:45 +0200 | From | Maxime Ripard <> | Subject | Re: [PATCH v4 02/11] clk: sunxi-ng: a64: Add max. rate constraint to video PLLs |
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On Tue, Sep 04, 2018 at 12:40:44PM +0800, Icenowy Zheng wrote: > Video PLLs on A64 can be set to higher rate that it is actually > supported by HW. > > Limit maximum rate to 1008 MHz. This is the maximum allowed rate by BSP > clock driver. Interestengly, user manual specifies maximum frequency to > be 600 MHz. Historically, this data was wrong in some user manuals for > other SoCs, so more faith is put in BSP clock driver. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Applied, thanks! Maxime
-- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com [unhandled content-type:application/pgp-signature] | |