Messages in this thread | | | Subject | Re: [PATCH V2 2/3] x86, perf: Add a separate Arch Perfmon v4 PMI handler | From | "Liang, Kan" <> | Date | Thu, 27 Sep 2018 09:53:28 -0400 |
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On 9/27/2018 8:51 AM, Peter Zijlstra wrote: > On Wed, Aug 08, 2018 at 12:12:07AM -0700, kan.liang@linux.intel.com wrote: >> @@ -4325,6 +4428,8 @@ __init int intel_pmu_init(void) >> x86_pmu.extra_regs = intel_skl_extra_regs; >> x86_pmu.pebs_aliases = intel_pebs_aliases_skl; >> x86_pmu.pebs_prec_dist = true; >> + x86_pmu.counter_freezing = disable_counter_freezing ? >> + false : true; >> /* all extra regs are per-cpu when HT is on */ >> x86_pmu.flags |= PMU_FL_HAS_RSP_1; >> x86_pmu.flags |= PMU_FL_NO_HT_SHARING; > > > How about so instead? It is very much tied to the perfmon version, not > the FMS. >
Yes, it matches the name of the handler. But the change as below is not sufficient. We have to temporarily disable counter_freezing in this patch for small core. The 3/3 patch will also be impact.
I will send V3 patch for these changes.
Thanks, Kan
> --- a/arch/x86/events/intel/core.c > +++ b/arch/x86/events/intel/core.c > @@ -4049,6 +4049,9 @@ __init int intel_pmu_init(void) > max((int)edx.split.num_counters_fixed, assume); > } > > + if (version >= 4) > + x86_pmu.counter_freezing = !disable_counter_freezing; > + > if (boot_cpu_has(X86_FEATURE_PDCM)) { > u64 capabilities; > > @@ -4428,8 +4431,6 @@ __init int intel_pmu_init(void) > x86_pmu.extra_regs = intel_skl_extra_regs; > x86_pmu.pebs_aliases = intel_pebs_aliases_skl; > x86_pmu.pebs_prec_dist = true; > - x86_pmu.counter_freezing = disable_counter_freezing ? > - false : true; > /* all extra regs are per-cpu when HT is on */ > x86_pmu.flags |= PMU_FL_HAS_RSP_1; > x86_pmu.flags |= PMU_FL_NO_HT_SHARING; >
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