lkml.org 
[lkml]   [2018]   [Sep]   [24]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH 4.18 222/235] drm/amd/pp: Send khz clock values to DC for smu7/8
    Date
    4.18-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Harry Wentland <harry.wentland@amd.com>

    [ Upstream commit c3cb424a086921f6bb0449b10d998352a756d6d5 ]

    The previous change wasn't covering smu 7 and 8 and therefore DC was
    seeing wrong clock values.

    This fixes an issue where the pipes seem to hang with a 4k DP and 1080p
    HDMI display.

    Fixes: c3df50abc84b ("drm/amd/pp: Convert clock unit to KHz as defined")
    Signed-off-by: Harry Wentland <harry.wentland@amd.com>
    Acked-by: Alex Deucher <alexander.deucher@amd.com>
    Cc:rex.zhu@amd.com
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 8 ++++----
    drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c | 6 +++---
    2 files changed, 7 insertions(+), 7 deletions(-)

    --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
    +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
    @@ -4555,12 +4555,12 @@ static int smu7_get_sclks(struct pp_hwmg
    return -EINVAL;
    dep_sclk_table = table_info->vdd_dep_on_sclk;
    for (i = 0; i < dep_sclk_table->count; i++)
    - clocks->clock[i] = dep_sclk_table->entries[i].clk;
    + clocks->clock[i] = dep_sclk_table->entries[i].clk * 10;
    clocks->count = dep_sclk_table->count;
    } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
    sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk;
    for (i = 0; i < sclk_table->count; i++)
    - clocks->clock[i] = sclk_table->entries[i].clk;
    + clocks->clock[i] = sclk_table->entries[i].clk * 10;
    clocks->count = sclk_table->count;
    }

    @@ -4592,7 +4592,7 @@ static int smu7_get_mclks(struct pp_hwmg
    return -EINVAL;
    dep_mclk_table = table_info->vdd_dep_on_mclk;
    for (i = 0; i < dep_mclk_table->count; i++) {
    - clocks->clock[i] = dep_mclk_table->entries[i].clk;
    + clocks->clock[i] = dep_mclk_table->entries[i].clk * 10;
    clocks->latency[i] = smu7_get_mem_latency(hwmgr,
    dep_mclk_table->entries[i].clk);
    }
    @@ -4600,7 +4600,7 @@ static int smu7_get_mclks(struct pp_hwmg
    } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
    mclk_table = hwmgr->dyn_state.vddc_dependency_on_mclk;
    for (i = 0; i < mclk_table->count; i++)
    - clocks->clock[i] = mclk_table->entries[i].clk;
    + clocks->clock[i] = mclk_table->entries[i].clk * 10;
    clocks->count = mclk_table->count;
    }
    return 0;
    --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
    +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
    @@ -1605,17 +1605,17 @@ static int smu8_get_clock_by_type(struct
    switch (type) {
    case amd_pp_disp_clock:
    for (i = 0; i < clocks->count; i++)
    - clocks->clock[i] = data->sys_info.display_clock[i];
    + clocks->clock[i] = data->sys_info.display_clock[i] * 10;
    break;
    case amd_pp_sys_clock:
    table = hwmgr->dyn_state.vddc_dependency_on_sclk;
    for (i = 0; i < clocks->count; i++)
    - clocks->clock[i] = table->entries[i].clk;
    + clocks->clock[i] = table->entries[i].clk * 10;
    break;
    case amd_pp_mem_clock:
    clocks->count = SMU8_NUM_NBPMEMORYCLOCK;
    for (i = 0; i < clocks->count; i++)
    - clocks->clock[i] = data->sys_info.nbp_memory_clock[clocks->count - 1 - i];
    + clocks->clock[i] = data->sys_info.nbp_memory_clock[clocks->count - 1 - i] * 10;
    break;
    default:
    return -1;

    \
     
     \ /
      Last update: 2018-09-24 14:48    [W:4.042 / U:0.028 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site