Messages in this thread | | | Date | Tue, 18 Sep 2018 15:23:08 +0200 (CEST) | From | Thomas Gleixner <> | Subject | Re: [patch 09/11] x86/vdso: Simplify the invalid vclock case |
| |
On Tue, 18 Sep 2018, Peter Zijlstra wrote: > On Tue, Sep 18, 2018 at 12:41:57PM +0200, Thomas Gleixner wrote: > > I still have one of the machines which is affected by this. > > Are we sure this isn't a load vs rdtsc reorder? Because if I look at the > current code:
The load order of last vs. rdtsc does not matter at all.
CPU0 CPU1
.... now0 = rdtsc_ordered(); ... tk->cycle_last = now0;
gtod->seq++; gtod->cycle_last = tk->cycle_last; ... gtod->seq++; seq_begin(gtod->seq); now1 = rdtsc_ordered();
So if the TSC on CPU1 is slightly behind the TSC on CPU0 then now1 can be smaller than cycle_last. The TSC sync stuff does not catch the small delta for unknown raisins. I'll go and find that machine and test that again.
Thanks,
tglx
| |