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SubjectRe: [PATCH v6 03/16] x86/cpu/mtrr: Support TOP_MEM2 and get MTRR number
On Mon, Sep 10, 2018 at 09:16:03PM +0800, Pu Wen wrote:
> The Hygon Dhyana CPU have a special magic MSR way to force WB for

From the last review round:

Also, it is "The ... CPU has a special..."

Please take your time and incorporate *all* review feedback - no need to
*rush* a new revision out and drop review feedback.

> memory >4GB, and support TOP_MEM2. Therefore, it is necessary to
> add Hygon Dhyana support in amd_special_default_mtrr().
>
> The number of variable MTRRs for Hygon is 2 as AMD's.
>
> Signed-off-by: Pu Wen <puwen@hygon.cn>
> ---
> arch/x86/kernel/cpu/mtrr/cleanup.c | 3 ++-
> arch/x86/kernel/cpu/mtrr/mtrr.c | 2 +-
> 2 files changed, 3 insertions(+), 2 deletions(-)

With that fixed:

Reviewed-by: Borislav Petkov <bp@suse.de>

--
Regards/Gruss,
Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

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