Messages in this thread | | | From | Anup Patel <> | Date | Mon, 10 Sep 2018 22:08:58 +0530 | Subject | Re: [PATCH v2 3/5] irqchip: RISC-V Local Interrupt Controller Driver |
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On Mon, Sep 10, 2018 at 10:05 PM, Christoph Hellwig <hch@infradead.org> wrote: > On Mon, Sep 10, 2018 at 10:02:09PM +0530, Anup Patel wrote: >> You are thinking very much in-context of SiFive CPUs only. > > No. I think in terms of the RISC-V spec. I could care less about > SiFive to be honest. > >> Lot of SOC vendors are trying to come-up with their own CPUs >> and RISC-V spec does not restrict the use of local interrupts. > > Yes, it does. > >> The mie/mip/sie/sip/uie/uip are all machine word size so on >> riscv64 we can theoretically have maximum 64 local interrupts. > > They could in theory IFF someone actually get the use case through > the riscv privileged spec working group.
Their is no point in having each and every possible local interrupts defined by RISC-V spec because some of these will be CPU implementation specific in which case these local interrupts will be described in platform specific DT passed to Linux.
Regards, Anup
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