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SubjectRe: [PATCH v3 09/12] RISC-V: User WRITE_ONCE instead of direct access
On Thu, Sep 06, 2018 at 01:05:32AM -0700, Atish Patra wrote:
> The secondary harts spin on couple of per cpu variables until both of
> these are non-zero so it's not necessary to have any ordering here.
> However, WRITE_ONCE should be used to avoid tearing.

We normally pair WRITE_ONCE with READ_ONCE. But it seems like the
reader side is in assembly code, so this should be ok:

Reviewed-by: Christoph Hellwig <hch@lst.de>

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