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    SubjectRe: [PATCH 2/3] x86, perf: Add a separate Arch Perfmon v4 PMI handler
    On Tue, Aug 07, 2018 at 11:29:54AM -0400, Liang, Kan wrote:
    > On 8/6/2018 2:35 PM, Peter Zijlstra wrote:
    > > On Mon, Aug 06, 2018 at 10:23:42AM -0700, kan.liang@linux.intel.com wrote:
    > > > @@ -2044,6 +2056,14 @@ static void intel_pmu_disable_event(struct perf_event *event)
    > > > if (unlikely(event->attr.precise_ip))
    > > > intel_pmu_pebs_disable(event);
    > > > + /*
    > > > + * We could disable freezing here, but doesn't hurt if it's on.
    > > > + * perf remembers the state, and someone else will likely
    > > > + * reinitialize.
    > > > + *
    > > > + * This avoids an extra MSR write in many situations.
    > > > + */
    > > > +
    > > > if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
    > > > intel_pmu_disable_fixed(hwc);
    > > > return;
    > > > @@ -2119,6 +2139,11 @@ static void intel_pmu_enable_event(struct perf_event *event)
    > > > if (event->attr.exclude_guest)
    > > > cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
    > > > + if (x86_pmu.counter_freezing && !cpuc->frozen_enabled) {
    > > > + enable_counter_freeze();
    > > > + cpuc->frozen_enabled = 1;
    > > > + }
    > > > +
    > > > if (unlikely(event_is_checkpointed(event)))
    > > > cpuc->intel_cp_status |= (1ull << hwc->idx);
    > >
    > > Why here? That doesn't really make sense; should this not be in
    > > intel_pmu_cpu_starting() or something?
    >
    >
    > For Goldmont Plus, the counter freezing feature can be re-enabled at
    > run-time by loading a newer microcode.
    > We need to check the x86_pmu.counter_freezing every time.

    Blergh, just don't go there. If we start with the wrong ucode, leave it
    disabled.

    We do that for most ucode stuff.

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