Messages in this thread Patch in this message | | | From | Marcel Ziswiler <> | Subject | [PATCH v2 24/34] ARM: tegra: apalis_t30: get rid of fake clocks simple bus | Date | Fri, 31 Aug 2018 18:38:06 +0200 |
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From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Get rid of the fake clocks simple bus and use node names as per the actual schematics.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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Changes in v2: - Get rid of fake clocks simple bus as suggested by Rob.
arch/arm/boot/dts/tegra30-apalis.dtsi | 27 +++++++++------------------ 1 file changed, 9 insertions(+), 18 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index 6d6f17422478..d80101df2228 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -1097,25 +1097,16 @@ mmc-ddr-1_8v; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clk@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: xtal1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; - clk16m: clk@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <16000000>; - clock-output-names = "clk16m"; - }; + clk16m: osc4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; }; reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll { -- 2.14.4
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