| Subject | Re: [RFC PATCH v3 12/24] x86/mm: Modify ptep_set_wrprotect and pmdp_set_wrprotect for _PAGE_DIRTY_SW | From | Dave Hansen <> | Date | Fri, 31 Aug 2018 09:29:51 -0700 |
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On 08/30/2018 07:38 AM, Yu-cheng Yu wrote: > + * Some processors can start a write, but ending up seeing > + * a read-only PTE by the time they get to the Dirty bit. > + * In this case, they will set the Dirty bit, leaving a > + * read-only, Dirty PTE which looks like a Shadow Stack PTE. > + * > + * However, this behavior has been improved and will not occur > + * on processors supporting Shadow Stacks. Without this > + * guarantee, a transition to a non-present PTE and flush the > + * TLB would be needed.
Did we publicly document this behavior anywhere? I can't seem to find it.
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