Messages in this thread | | | Date | Sun, 26 Aug 2018 12:25:09 +0200 (CEST) | From | Thomas Gleixner <> | Subject | Re: [PATCH v2 2/2] x86/pae: use 64 bit atomic xchg function in native_ptep_get_and_clear |
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On Tue, 21 Aug 2018, Juergen Gross wrote:
> Using only 32-bit writes for the pte will result in an intermediate > L1TF vulnerable PTE. When running as a Xen PV guest this will at once > switch the guest to shadow mode resulting in a loss of performance. > > Use arch_atomic64_xchg() instead which will perform the requested > operation atomically with all 64 bits. > > Some performance considerations according to: > > https://software.intel.com/sites/default/files/managed/ad/dc/Intel-Xeon-Scalable-Processor-throughput-latency.pdf > > The main number should be the latency, as there is no tight loop around > native_ptep_get_and_clear(). > > "lock cmpxchg8b" has a latency of 20 cycles, while "lock xchg" (with a > memory operand) isn't mentioned in that document. "lock xadd" (with xadd > having 3 cycles less latency than xchg) has a latency of 11, so we can > assume a latency of 14 for "lock xchg". > > Signed-off-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
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