Messages in this thread | | | Subject | Re: [PATCH 3/4] mm/tlb, x86/mm: Support invalidating TLB caches for RCU_TABLE_FREE | From | Benjamin Herrenschmidt <> | Date | Thu, 23 Aug 2018 15:21:30 +1000 |
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On Wed, 2018-08-22 at 22:11 -0700, Linus Torvalds wrote: > On Wed, Aug 22, 2018 at 9:54 PM Benjamin Herrenschmidt <benh@au1.ibm.com> wrote: > > > > > > So we do need a different flush instruction for the page tables vs. the > > normal TLB pages. > > Right. ARM wants it too. x86 is odd in that a regular "invlpg" already > invalidates all the internal tlb cache nodes. > > So the "new world order" is exactly that patch that PeterZ sent you, that adds a > > + unsigned int freed_tables : 1; >
.../...
> So instead, when you get to the actual "tlb_flush(tlb)", you do > exactly that - flush the tlb. And the mmu_gather structure shows you > how much you need to flush. If you see that "freed_tables" is set, > then you know that you need to also do the special instruction to > flush the inner level caches. The range continues to show the page > range.
Yup. That looks like a generic version of the "need_flush_all" flag we have, which is fine by us.
Just don't blame powerpc for all the historical crap :-)
Cheers, Ben.
> > Linus
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