Messages in this thread | | | Date | Mon, 20 Aug 2018 16:18:10 +0200 | From | Maxime Ripard <> | Subject | Re: [PATCH] clk: sunxi-ng: sun50i: h6: Add 2x fixed post-divider to MMC module clocks |
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On Mon, Aug 20, 2018 at 09:40:13PM +0800, Icenowy Zheng wrote: > On the H6, the MMC module clocks are fixed in the new timing mode, > i.e. they do not have a bit to select the mode. These clocks have > a 2x divider somewhere between the clock and the MMC module. > > To be consistent with other SoCs supporting the new timing mode, > we model the 2x divider as a fixed post-divider on the MMC module > clocks. > > This patch adds the post-dividers to the MMC clocks, following the > approach on A64. > > Fixes: 542353ea ("clk: sunxi-ng: add support for the Allwinner H6 CCU") > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Thanks! Maxime
-- Maxime Ripard, Bootlin (formerly Free Electrons) Embedded Linux and Kernel engineering https://bootlin.com [unhandled content-type:application/pgp-signature] | |