Messages in this thread | | | From | Vitaly Kuznetsov <> | Subject | Re: [PATCH RFC] x86/kvm/lapic: always disable MMIO interface in x2APIC mode | Date | Thu, 02 Aug 2018 15:30:15 +0200 |
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Paolo Bonzini <pbonzini@redhat.com> writes:
> On 30/07/2018 11:14, Vitaly Kuznetsov wrote: >> Paolo Bonzini <pbonzini@redhat.com> writes: >> >>> On 27/07/2018 18:48, Jim Mattson wrote: >>>> On a physical machine, I would expect the default local APIC page to >>>> fall in the PCI hole, so it would be correct to sink writes and to >>>> return all ones for reads. Does qemu implement a PCI hole, and does >>>> this address fall into it? >>> >>> It does implement a PCI hole, but when using the kernel LAPIC it expects >>> that only devices write to that range; therefore that address doesn't >>> fall into the PCI hole, and instead it generates an MSIs. >> >> Yes, and that's why I believe it's correct to never forward lapic >> reads/writes from KVM to userspace when lapic is in kernel. >> >> "RFC" was mostly about the inconsistency with the case when APIC access >> page is in use. To be 100% correct I would suggest to somehow make it >> behave like MMIO hole in case we're in x2APIC/disabled mode too. >> > > FWIW it is possible to move the MSI memory region from system memory to > the PCI address space in QEMU, however I'm worried about backwards > compatibility. >
You know better :-)
> Vitaly, perhaps you could resubmit this patch, and provide a > KVM_CAP_DISABLE_QUIRKS switch that would make apic_mmio_{read,write} > return -EOPNOTSUPP in this case?
Just to make sure I understand,
we introduce a KVM_QUIRK_LAPIC_DISABLED_MMIO bit and will be emulating MMIO hole in KVM till Qemu is able to deal with reads/writes passed to it correctly?
-- Vitaly
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