Messages in this thread | | | Date | Thu, 2 Aug 2018 11:59:11 +0200 | From | Christoph Hellwig <> | Subject | Re: [PATCH 5/9] RISC-V: implement low-level interrupt handling |
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On Thu, Aug 02, 2018 at 11:48:55AM +0200, Thomas Gleixner wrote: > > diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S > > index 9aaf6c986771..fa2c08e3c05e 100644 > > --- a/arch/riscv/kernel/entry.S > > +++ b/arch/riscv/kernel/entry.S > > @@ -168,8 +168,8 @@ ENTRY(handle_exception) > > > > /* Handle interrupts */ > > move a0, sp /* pt_regs */ > > - REG_L a1, handle_arch_irq > > - jr a1 > > + move a1, s4 /* scause */ > > + tail do_IRQ > > What's the reason for doing the whole exception dance in ASM ?
I'll let Palmer defend it. But for now I just want minimal changes to actually get a booting system..
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