Messages in this thread Patch in this message | | | From | Alan Douglas <> | Subject | [RFC PATCH 1/2] dt-bindings: phy: Document cadence Sierra PHY bindings | Date | Fri, 17 Aug 2018 13:31:20 +0100 |
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Add DT binding documentation for Sierra PHY. The PHY supports a number of different protocols, including PCIe and USB. The number of lanes can also be configured.
Signed-off-by: Alan Douglas <adouglas@cadence.com> --- .../devicetree/bindings/phy/cdns-sierra-phy.txt | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt b/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt new file mode 100644 index 0000000..846bdfc --- /dev/null +++ b/Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt @@ -0,0 +1,29 @@ +Cadence Sierra PHY +----------------------- + +Required properties: + - compatible: cdns,sierra-phy + - clocks: Must contain an entry in clock-names. + See ../clocks/clock-bindings.txt for details. + - clock-names: Must be "phy_clk" + - resets: Must contain an entry for each in reset-names. + See ../reset/reset.txt for details. + - reset-names: Must include "sierra_reset" and "sierra_apb" + "sierra_reset" must control the reset line to the PHY + "sierra_apb" must control the reset line to the APB PHY interface + - #phy-cells: must be 2 + - reg : register range for the PHY + - reg-names: Must be "reg" + + +Example: + pcie_phy4: pcie-phy4@fd240000 { + compatible = "cdns,sierra-phy"; + reg = <0x0 0xfd240000 0x0 0x40000>; + reg-names = "reg"; + #phy-cells = <2>; + resets = <&dummyrst2 0>, <&dummyrst3 0>; + reset-names = "sierra_reset","sierra_apb"; + clocks = <&phyclock>; + clock-names = "phy_clk"; + }; -- 1.9.0
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