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    Subject[PATCH 4.17 46/97] x86/cpufeatures: Add detection of L1D cache flush support.
    Date
    4.17-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>

    commit 11e34e64e4103955fc4568750914c75d65ea87ee upstream

    336996-Speculative-Execution-Side-Channel-Mitigations.pdf defines a new MSR
    (IA32_FLUSH_CMD) which is detected by CPUID.7.EDX[28]=1 bit being set.

    This new MSR "gives software a way to invalidate structures with finer
    granularity than other architectual methods like WBINVD."

    A copy of this document is available at
    https://bugzilla.kernel.org/show_bug.cgi?id=199511

    Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
    Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    arch/x86/include/asm/cpufeatures.h | 1 +
    1 file changed, 1 insertion(+)

    --- a/arch/x86/include/asm/cpufeatures.h
    +++ b/arch/x86/include/asm/cpufeatures.h
    @@ -340,6 +340,7 @@
    #define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */
    #define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
    #define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */
    +#define X86_FEATURE_FLUSH_L1D (18*32+28) /* Flush L1D cache */
    #define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
    #define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* "" Speculative Store Bypass Disable */


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