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SubjectRe: [PATCH] perf/x86/amd/uncore: Set ThreadMask and SliceMask for L3 Cache perf events
Hi Janakarajan,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on tip/perf/core]
[also build test WARNING on v4.18 next-20180813]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url: https://github.com/0day-ci/linux/commits/Janakarajan-Natarajan/perf-x86-amd-uncore-Set-ThreadMask-and-SliceMask-for-L3-Cache-perf-events/20180814-064324
config: i386-randconfig-x002-201832 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-16) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386

All warnings (new ones prefixed by >>):

In file included from include/linux/perf_event.h:25:0,
from arch/x86//events/amd/uncore.c:11:
arch/x86//events/amd/uncore.c: In function 'amd_uncore_event_init':
>> arch/x86/include/asm/perf_event.h:51:11: warning: left shift count >= width of type [-Wshift-count-overflow]
((0xFUL) << AMD64_L3_SLICE_SHIFT)
^
>> arch/x86//events/amd/uncore.c:218:19: note: in expansion of macro 'AMD64_L3_SLICE_MASK'
hwc->config |= (AMD64_L3_SLICE_MASK | AMD64_L3_THREAD_MASK);
^~~~~~~~~~~~~~~~~~~
arch/x86/include/asm/perf_event.h:55:12: warning: left shift count >= width of type [-Wshift-count-overflow]
((0xFFUL) << AMD64_L3_THREAD_SHIFT)
^
>> arch/x86//events/amd/uncore.c:218:41: note: in expansion of macro 'AMD64_L3_THREAD_MASK'
hwc->config |= (AMD64_L3_SLICE_MASK | AMD64_L3_THREAD_MASK);
^~~~~~~~~~~~~~~~~~~~
--
In file included from include/linux/perf_event.h:25:0,
from arch/x86/events/amd/uncore.c:11:
arch/x86/events/amd/uncore.c: In function 'amd_uncore_event_init':
>> arch/x86/include/asm/perf_event.h:51:11: warning: left shift count >= width of type [-Wshift-count-overflow]
((0xFUL) << AMD64_L3_SLICE_SHIFT)
^
arch/x86/events/amd/uncore.c:218:19: note: in expansion of macro 'AMD64_L3_SLICE_MASK'
hwc->config |= (AMD64_L3_SLICE_MASK | AMD64_L3_THREAD_MASK);
^~~~~~~~~~~~~~~~~~~
arch/x86/include/asm/perf_event.h:55:12: warning: left shift count >= width of type [-Wshift-count-overflow]
((0xFFUL) << AMD64_L3_THREAD_SHIFT)
^
arch/x86/events/amd/uncore.c:218:41: note: in expansion of macro 'AMD64_L3_THREAD_MASK'
hwc->config |= (AMD64_L3_SLICE_MASK | AMD64_L3_THREAD_MASK);
^~~~~~~~~~~~~~~~~~~~

vim +51 arch/x86/include/asm/perf_event.h

39
40 #define AMD64_EVENTSEL_INT_CORE_SEL_SHIFT 37
41 #define AMD64_EVENTSEL_INT_CORE_SEL_MASK \
42 (0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT)
43
44 #define AMD64_EVENTSEL_EVENT \
45 (ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
46 #define INTEL_ARCH_EVENT_MASK \
47 (ARCH_PERFMON_EVENTSEL_UMASK | ARCH_PERFMON_EVENTSEL_EVENT)
48
49 #define AMD64_L3_SLICE_SHIFT 48
50 #define AMD64_L3_SLICE_MASK \
> 51 ((0xFUL) << AMD64_L3_SLICE_SHIFT)
52

---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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