Messages in this thread | | | Subject | Re: [PATCH 3/3] PCI/portdrv: Add support for sharing xilinx controller irq with AER | From | Sinan Kaya <> | Date | Wed, 1 Aug 2018 11:05:09 -0700 |
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On 8/1/2018 9:44 AM, Bharat Kumar Gogada wrote: > Xilinx ZynqMP PS PCIe does not report AER interrupts using Advanced > Error Interrupt Message Number. The controller has dedicated interrupt line > for reporting PCIe errors along with AER. > > Using dedicated controller irq number for AER which is shared with misc > interrupt handler in pcie-xilinx-nwl. This irq number is set > using PCI quirk. > > Signed-off-by: Bharat Kumar Gogada<bharat.kumar.gogada@xilinx.com> > --- > drivers/pci/pcie/portdrv_core.c | 4 ++++ > 1 files changed, 4 insertions(+), 0 deletions(-) > > diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c > index e0261ad..fa9150e 100644 > --- a/drivers/pci/pcie/portdrv_core.c > +++ b/drivers/pci/pcie/portdrv_core.c > @@ -264,6 +264,10 @@ static int pcie_device_init(struct pci_dev *pdev, int service, int irq) > int retval; > struct pcie_device *pcie; > struct device *device; > +#if defined(CONFIG_ARCH_ZYNQMP) && defined(CONFIG_PCIE_XILINX_NWL) > + if (service == PCIE_PORT_SERVICE_AER && pdev->sysdata) > + irq = *(int *)pdev->sysdata; > +#endif >
I remember seeing a similar patch before. The patch above looks ugly to be honest. Need to find a way to generalize this. Can you search the mailing list archive to find out what the history is?
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