Messages in this thread | | | From | Linus Walleij <> | Date | Sun, 29 Jul 2018 22:44:17 +0200 | Subject | Re: [PATCH 1/2] pinctrl/amd: only handle irq if it is pending and unmasked |
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On Tue, Jul 17, 2018 at 2:57 AM Daniel Kurtz <djkurtz@chromium.org> wrote:
> The AMD pinctrl driver demultiplexes GPIO interrupts and fires off their > individual handlers. > > If one of these GPIO irqs is configured as a level interrupt, and its > downstream handler is a threaded ONESHOT interrupt, the GPIO interrupt > source is masked by handle_level_irq() until the eventual return of the > threaded irq handler. During this time the level GPIO interrupt status > will still report as high until the actual gpio source is cleared - both > in the individual GPIO interrupt status bit (INTERRUPT_STS_OFF) and in > its corresponding "WAKE_INT_STATUS_REG" bit. > > Thus, if another GPIO interrupt occurs during this time, > amd_gpio_irq_handler() will see that the (masked-and-not-yet-cleared) > level irq is still pending and incorrectly call its handler again. > > To fix this, have amd_gpio_irq_handler() check for both interrupts status > and mask before calling generic_handle_irq(). > > Note: Is it possible that this bug was the source of the interrupt storm > on Ryzen when using chained interrupts before commit ba714a9c1dea85 > ("pinctrl/amd: Use regular interrupt instead of chained")? > > Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Patch applied with TGLX ACK.
Yours, Linus Walleij
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