Messages in this thread | | | Subject | Re: [PATCH 3/3] clk: meson: clk-pll: drop hard-coded rates from pll tables | From | jbrunet@baylibre ... | Date | Thu, 26 Jul 2018 10:48:12 +0200 |
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On Sat, 2018-07-21 at 23:34 +0200, Martin Blumenstingl wrote: > On Sat, Jul 21, 2018 at 10:46 PM Jerome Brunet <jbrunet@baylibre.com> wrote: > > > > On Sat, 2018-07-21 at 22:16 +0200, Martin Blumenstingl wrote: > > > > We could even add ranges instead of table when we know the PLL supports a well-known continuous dividers range. > > > > > > I had a look at the sys_pll settings on Meson8b, here's what > > > Meson8/Meson8b/Meson8m2 support for sys_pll: > > > - 50..74 > > > - 76 > > > - 78 > > > - 80 > > > - 82 > > > - 84 > > > - 86 > > > - 88 > > > - 90 > > > - 92 > > > - 94 > > > - 96 > > > - 98 > > > > Are those values with the same predivider (n) value ? > > yes, all are using n = 1
The table proposed in this patch keeps things the way they were before the change. We could extend the table with these values in a follow up patch.
If those value are with n=1, then I would guess that odd values from 75 to 97 work as well.
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