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    Subject[PATCH 4.4 097/107] x86/bugs: Rename SSBD_NO to SSB_NO
    Date
    4.4-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>

    commit 240da953fcc6a9008c92fae5b1f727ee5ed167ab upstream

    The "336996 Speculative Execution Side Channel Mitigations" from
    May defines this as SSB_NO, hence lets sync-up.

    Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
    Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
    Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    Signed-off-by: Srivatsa S. Bhat <srivatsa@csail.mit.edu>
    Reviewed-by: Matt Helsley (VMware) <matt.helsley@gmail.com>
    Reviewed-by: Alexey Makhalov <amakhalov@vmware.com>
    Reviewed-by: Bo Gan <ganb@vmware.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---

    arch/x86/include/asm/msr-index.h | 2 +-
    arch/x86/kernel/cpu/common.c | 2 +-
    2 files changed, 2 insertions(+), 2 deletions(-)

    --- a/arch/x86/include/asm/msr-index.h
    +++ b/arch/x86/include/asm/msr-index.h
    @@ -58,7 +58,7 @@
    #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a
    #define ARCH_CAP_RDCL_NO (1 << 0) /* Not susceptible to Meltdown */
    #define ARCH_CAP_IBRS_ALL (1 << 1) /* Enhanced IBRS support */
    -#define ARCH_CAP_SSBD_NO (1 << 4) /*
    +#define ARCH_CAP_SSB_NO (1 << 4) /*
    * Not susceptible to Speculative Store Bypass
    * attack, so no Speculative Store Bypass
    * control required.
    --- a/arch/x86/kernel/cpu/common.c
    +++ b/arch/x86/kernel/cpu/common.c
    @@ -881,7 +881,7 @@ static void __init cpu_set_bug_bits(stru
    rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);

    if (!x86_match_cpu(cpu_no_spec_store_bypass) &&
    - !(ia32_cap & ARCH_CAP_SSBD_NO))
    + !(ia32_cap & ARCH_CAP_SSB_NO))
    setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);

    if (x86_match_cpu(cpu_no_speculation))

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